Datasheet > ADCLK954BCPZ-REEL7

ADCLK954BCPZ-REEL7

更新时间： 2024-01-02 23:43:18

品牌	Logo	应用领域
亚德诺 - ADI		半导体逻辑集成电路驱动时钟
页数	文件大小	规格书
12页	294K
描述
Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer

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ADCLK954

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Typical (Typ column) values are given for V_CC− V_EE= 3.3 V and T_A= 25°C, unless otherwise noted. Minimum (Min column) and maximum

(Max column) values are given over the full V_CC− V_EE= 3.3 V 10ꢀ and T_A= −40°C to +85°C variation, unless otherwise noted.

Table 1. Clock Inputs and Outputs

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

DC INPUT CHARACTERISTICS

Input Common-Mode Voltage

Input Differential Range

Input Capacitance

V_ICM

V_ID

C_IN

V_EE+ 1.5

0.4

V_CC− 0.1

3.4

V p-p

1.ꢀ V between input pins

0.4

Input Resistance

Single-Ended Mode

Differential Mode

Common Mode

Input Bias Current

Hysteresis

100

kΩ

μA

Open V_Tx

DC OUTPUT CHARACTERISTICS

Output Voltage High Level

Output Voltage Low Level

Output Voltage Differential

Reference Voltage

V_OH

V_OL

V_OD

V_REF

V_CC− 1.26

V_CC− 1.99

610

V_CC− 0.ꢀ6

V_CC− 1.54

960

50 Ω to (V_CC− 2.0 V)

Output Voltage

Output Resistance

(V_CC+ 1)/2

235

−500 μA to +500 μA

Table 2. Timing Characteristics

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

AC PERFORMANCE

Maximum Output Frequency

4.5

4.8

GHz

See Figure 4 for differential output voltage vs.

frequency, > 0.8 V differential output swing

Output Rise Time

Output Fall Time

Propagation Delay

Temperature Coefficient

Output-to-Output Skew¹

Part-to-Part Skew

t_R

t_F

t_PD

1ꢀ5

ꢀ5

210

245

fs/°C

20% to 80% measured differentially

V_ICM= 2 V, V_ID= 1.6 V p-p

V_ID= 1.6 V p-p

Additive Time Jitter

Integrated Random Jitter

Broadband Random Jitter²

Crosstalk-Induced Jitter³

CLOCK OUTPUT PHASE NOISE

Absolute Phase Noise

ꢀ5

fs rms

BW = 12 kHz − 20 MHz, CLK = 1 GHz

V_ID= 1.6 V p-p, 8 V/ns, V_ICM= 2 V

Input slew rate > 1 V/ns (see Figure 11, the

phase noise plot, for more details)

f_IN= 1 GHz

−119

−134

−145

−150

dBc/Hz @100 Hz offset

dBc/Hz @1 kHz offset

dBc/Hz @10 kHz offset

dBc/Hz @100 kHz offset

dBc/Hz >1 MHz offset

¹The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.

²Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.

³This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.

Rev. A | Page 3 of 12

1 234 5 6 7...12

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ADCLK954BCPZ-REEL7 替代型号

型号	品牌	替代类型	描述	数据表
ADCLK954BCPZ	ADI	完全替代	Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer

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