Datasheet > ADCLK954BCPZ-REEL7

ADCLK954BCPZ-REEL7

更新时间： 2024-01-29 11:08:06

品牌	Logo	应用领域
亚德诺 - ADI		半导体逻辑集成电路驱动时钟
页数	文件大小	规格书
12页	294K
描述
Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer

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ADCLK954BCPZ-REEL7 数据手册

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ADCLK954

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN_SEL

CLK0

30 V

29 Q4

28 Q4

27 Q5

26 Q5

25 Q6

24 Q6

23 Q7

22 Q7

REF

V 0

ADCLK954

TOP VIEW

(Not to Scale)

CLK1

V 1

REF

NOTES

1. EPAD MUST BE SOLDERED TO V POWER PLANE.

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

IN_SEL

CLK0

Description

Input Select. Logic 0 selects CLK0 and

Differential Input (Positive) 0.

inputs. Logic 1 selects CLK1 and

inputs.

CLK1

CLK0

Differential Input (Negative) 0.

V_REF

V_T0

Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and

inputs.

CLK0

Center Tap. Center tap of a 100 ꢂ input resistor for CLK0 and

Differential Input (Positive) 1.

Differential Input (Negative) 1.

inputs.

CLK0

ꢀ

CLK1

V_T1

Center Tap. Center tap of a 100 ꢂ input resistor for CLK1 and

inputs.

CLK1

V_REF

Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and

Negative Supply Pin.

inputs.

CLK1

V_EE

11, 20, 21,

30, 31, 40

V_CC

Positive Supply Pin.

12, 13

14, 15

16, 1ꢀ

18, 19

22, 23

24, 25

26, 2ꢀ

28, 29

32, 33

34, 35

36, 3ꢀ

38, 39

(41)

, Q11

, Q10

Differential LVPECL Outputs.

EPAD must be connected to V_EE.

Q11

Q10

, Q9

Qꢀ

, Q8

, Qꢀ

, Q6

, Q5

, Q4

, Q3

, Q2

, Q1

, Q0

EPAD

Rev. A | Page 6 of 12

1...3 4 567 8 9...12

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