ADCLK946

更新时间： 2024-02-22 14:53:05

品牌	Logo	应用领域
亚德诺 - ADI		时钟
页数	文件大小	规格书
12页	354K
描述
Six LVPECL Outputs, SiGe Clock Fanout Buffer

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技术参数
数据手册

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ADCLK946 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC24,.16SQ,20	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.83
Samacsys Confidence：	3	Samacsys Status：	Released
Samacsys PartID：	579004	Samacsys Pin Count：	25
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Quad Flat No-Lead
Samacsys Footprint Name：	CP-24-2-+-+	Samacsys Released Date：	2017-01-11 11:21:59
Is Samacsys：	N	系列：	946
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-XQCC-N24
JESD-609代码：	e3	长度：	4 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	6
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC24,.16SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	Prop。Delay @ Nom-Sup：	0.22 ns
传播延迟（tpd）：	0.22 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.28 ns	座面最大高度：	1 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	2.97 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	4 mm	Base Number Matches：	1

ADCLK946 数据手册

ADCLK946

FUNCTIONAL DESCRIPTION

Thevenin-equivalent termination uses a resistor network to

CLOCK INPUTS

provide 50 Ω termination to a dc voltage that is below V_OLof

the LVPECL driver. In this case, VS_DRV on the ADCLK946

should equal V_CCof the receiving buffer. Although the resistor

combination shown in Figure 15 results in a dc bias point of

VS_DRV − 2 V, the actual common-mode voltage is VS_DRV −

1.3 V because there is additional current flowing from the

ADCLK946 LVPECL driver through the pull-down resistor.

The ADCLK946 accepts a differential clock input and distributes it

to all six LVPECL outputs. The maximum specified frequency is

the point at which the output voltage swing is 50ꢀ of the standard

LVPECL swing (see Figure 4).

The device has a differential input equipped with center-tapped,

differential, 100 Ω on-chip termination resistors. The input accepts

dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and

ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A V_REFpin

is available for biasing ac-coupled inputs (see Figure 1).

LVPECL Y-termination is an elegant termination scheme that

uses the fewest components and offers both odd- and even-mode

impedance matching. Even-mode impedance matching is an

important consideration for closely coupled transmission lines

at high frequencies. Its main drawback is that it offers limited

flexibility for varying the drive strength of the emitter-follower

LVPECL driver. This can be an important consideration when

driving long trace lengths but is usually not an issue.

Maintain the differential input voltage swing from approximately

400 mV p-p to no more than 3.4 V p-p. See Figure 14 through

Figure 17 for various clock input termination schemes.

Output jitter performance is degraded by an input slew rate

below 1 V/ns, as shown in Figure 12. The ADCLK946 is

specifically designed to minimize added random jitter over a

wide input slew rate range. Whenever possible, clamp excessively

large input signals with fast Schottky diodes because attenuators

reduce the slew rate. Input signal runs of more than a few

centimeters should be over low loss dielectrics or cables with

good high frequency characteristics.

VS_DRV

= VS_DRV

ADCLK946

= 50Ω

50Ω

– 2V

LVPECL

Figure 14. DC-Coupled, 3.3 V LVPECL

CLOCK OUTPUTS

VS_DRV

The specified performance necessitates using proper trans-

mission line terminations. The LVPECL outputs of the

ADCLK946 are designed to directly drive 800 mV into a 50 Ω

cable or into microstrip/stripline transmission lines terminated

with 50 Ω referenced to V_CC− 2 V, as shown in Figure 14. The

LVPECL output stage is shown in Figure 13. The outputs are

designed for best transmission line matching. If high speed

signals must be routed more than a centimeter, either the

microstrip or the stripline technique is required to ensure

proper transition times and to prevent excessive output ringing

and pulse-width-dependent, propagation delay dispersion.

ADCLK946

VS_DRV

127Ω

50Ω

SINGLE-ENDED

(NOT COUPLED)

LVPECL

50Ω

83Ω

Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination

VS_DRV

= VS_DRV

ADCLK946

= 50Ω

50Ω

LVPECL

= 50Ω

Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination

VS_DRV

ADCLK946

0.1nF

100Ω DIFFERENTIAL

(COUPLED)

100Ω

LVPECL

0.1nF

TRANSMISSION LINE

200Ω

Figure 13. Simplified Schematic Diagram of

the LVPECL Output Stage

Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line

Figure 14 through Figure 17 depict various LVPECL output

termination schemes. When dc-coupled, V_CCof the receiving

buffer should match the VS_DRV.

Rev. 0 | Page 9 of 12

1...6 7 8910 11 12

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与ADCLK946相关器件

型号	品牌	描述	获取价格	数据表
ADCLK946/PCBZ	ADI	Six LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK946BCPZ	ADI	Six LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK946BCPZ-REEL7	ADI	Six LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK948	ADI	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK948/PCBZ	ADI	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格
ADCLK948BCPZ	ADI	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer	获取价格

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