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ADCLK946 PDF预览

ADCLK946

更新时间: 2024-02-20 10:26:30
品牌 Logo 应用领域
亚德诺 - ADI 时钟
页数 文件大小 规格书
12页 354K
描述
Six LVPECL Outputs, SiGe Clock Fanout Buffer

ADCLK946 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC24,.16SQ,20针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.83
Samacsys Confidence:3Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/579004.3.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=579004
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=5790043D View:https://componentsearchengine.com/viewer/3D.php?partID=579004
Samacsys PartID:579004Samacsys Image:https://componentsearchengine.com/Images/9/ADCLK946BCPZ.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/3/ADCLK946BCPZ.jpgSamacsys Pin Count:25
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:CP-24-2-+-+Samacsys Released Date:2017-01-11 11:21:59
Is Samacsys:N系列:946
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:24实输出次数:6
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:0.22 ns
传播延迟(tpd):0.22 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.28 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BIPOLAR
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:4 mmBase Number Matches:1

ADCLK946 数据手册

 浏览型号ADCLK946的Datasheet PDF文件第3页浏览型号ADCLK946的Datasheet PDF文件第4页浏览型号ADCLK946的Datasheet PDF文件第5页浏览型号ADCLK946的Datasheet PDF文件第7页浏览型号ADCLK946的Datasheet PDF文件第8页浏览型号ADCLK946的Datasheet PDF文件第9页 
ADCLK946  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
PIN 1  
INDICATOR  
V
CLK  
CLK  
1
2
3
4
5
6
18 V  
EE  
CC  
17 Q2  
16 Q2  
15 Q3  
14 Q3  
ADCLK946  
V
TOP VIEW  
REF  
V
V
(Not to Scale)  
T
13 V  
EE  
CC  
NOTES:  
1. EXPOSED PADDLE MUST BE CONNECTED TO V  
.
EE  
Figure 2. Pin Configuration  
Table 6. Pin Function Descriptions  
Pin No.  
1, 6, ꢀ, 12, 19  
2
Mnemonic  
Description  
VEE  
CLK  
CLK  
Negative Supply Pin.  
Differential Input (Positive).  
Differential Input (Negative).  
3
4
VREF  
Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs.  
5
VT  
Center Tap. This pin provides the center tap of a 100 Ω input resistor for CLK and CLK inputs.  
Differential LVPECL Outputs.  
8, 9  
Q5, Q5  
Q4, Q4  
VCC  
Q3, Q3  
Q2, Q2  
Q1, Q1  
Q0, Q0  
EPAD  
10, 11  
13, 18, 24  
14, 15  
16, 1ꢀ  
20, 21  
22, 23  
Differential LVPECL Outputs.  
Positive Supply Pin.  
Differential LVPECL Outputs.  
Differential LVPECL Outputs.  
Differential LVPECL Outputs.  
Differential LVPECL Outputs.  
EPAD must be soldered to VEE.  
Rev. 0 | Page 6 of 12  
 

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