ADCLK944BCPZ-R7

更新时间： 2024-01-16 16:07:52

品牌	Logo	应用领域
亚德诺 - ADI		时钟驱动器逻辑集成电路 PC
页数	文件大小	规格书
12页	217K
描述
2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer

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技术参数
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ADCLK944BCPZ-R7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	16
Reach Compliance Code：	unknown	风险等级：	5.74
Is Samacsys：	N	系列：	2400
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-PQCC-N16
JESD-609代码：	e3	长度：	3 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	湿度敏感等级：	NOT APPLICABLE
功能数量：	1	反相输出次数：
端子数量：	16	实输出次数：	4
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	0.13 ns
认证状态：	COMMERCIAL	Same Edge Skew-Max（tskwd）：	0.015 ns
座面最大高度：	0.8 mm	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	3 mm	最小 fmax：	6200 MHz
Base Number Matches：	1

ADCLK944BCPZ-R7 数据手册

ADCLK944

THEORY OF OPERATION

Figure 13 through Figure 16 depict various LVPECL output

termination schemes. When dc-coupled, V_CCof the receiving

buffer should match VS_DRV.

CLOCK INPUTS

The ADCLK944 accepts a differential clock input and distrib-

utes it to all four LVPECL outputs. The maximum specified

frequency is the point at which the output voltage swing is 50%

of the standard LVPECL swing (see Figure 4).

VS_DRV

= VS_DRV

LVPECL

ADCLK944

= 50Ω

50Ω

– 2V

The device has a differential input equipped with center-tapped,

differential, 100 Ω on-chip termination resistors. The input can

accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended,

3.3 V operation only), and ac-coupled 1.8 V CMOS, LVDS, and

LVPECL inputs. A V_REFpin is available for biasing ac-coupled

inputs (see Figure 20 and Figure 21).

= 50Ω

Figure 13. DC-Coupled, 3.3 V LVPECL

Thevenin-equivalent termination uses a resistor network to provide

50 Ω termination to a dc voltage that is below V_OLof the LVPECL

driver. In this case, VS_DRV on the ADCLK944 should equal

Maintain the differential input voltage swing from approxi-

mately 400 mV p-p to no more than 3.4 V p-p. See Figure 18

through Figure 21 for various clock input termination schemes.

V_CCof the receiving buffer. Although the resistor combination

shown in Figure 14 results in a dc bias point of VS_DRV − 2 V,

the actual common-mode voltage is VS_DRV − 1.3 V because

there is additional current flowing from the ADCLK944 LVPECL

driver through the pull-down resistor.

Output jitter performance is significantly degraded by an input

slew rate below 1 V/ns, as shown in Figure 11. The ADCLK944

is specifically designed to minimize added random jitter over a

wide input slew rate range. Whenever possible, clamp excessively

large input signals with fast Schottky diodes because attenuators

reduce the slew rate. Input signal runs of more than a few centi-

meters should be over low loss dielectrics or cables with good

high frequency characteristics.

VS_DRV

ADCLK944

VS_DRV

127Ω

50Ω

SINGLE-ENDED

(NOT COUPLED)

LVPECL

50Ω

CLOCK OUTPUTS

83Ω

The specified performance necessitates using proper transmis-

sion line terminations. The LVPECL outputs of the ADCLK944

are designed to directly drive 800 mV into a 50 Ω cable or into

microstrip/stripline transmission lines terminated with 50 Ω

referenced to V_CC− 2 V, as shown in Figure 13. The LVPECL

output stage is shown in Figure 12. The outputs are designed

for best transmission line matching. If high speed signals must

be routed more than a centimeter, either the microstrip or the

stripline technique is required to ensure proper transition times

and to prevent excessive output ringing and pulse-width-dependent

propagation delay dispersion.

Figure 14. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination

LVPECL Y-termination (see Figure 15) is an elegant termination

scheme that uses the fewest components and offers both odd-

and even-mode impedance matching. Even-mode impedance

matching is an important consideration for closely coupled trans-

mission lines at high frequencies. Its main drawback is that it offers

limited flexibility for varying the drive strength of the emitter-

follower LVPECL driver. This can be an important consideration

when driving long trace lengths but is usually not an issue.

VS_DRV

= VS_DRV

ADCLK944

= 50Ω

50Ω

LVPECL

Figure 15. DC-Coupled, 3.3 V LVPECL Y-Termination

VS_DRV

ADCLK944

0.1nF

100Ω DIFFERENTIAL

(COUPLED)

100Ω

LVPECL

0.1nF

TRANSMISSION LINE

200Ω

Figure 12. Simplified Schematic Diagram

of the LVPECL Output Stage

Figure 16. AC-Coupled LVPECL with Parallel Transmission Line

Rev. 0 | Page 9 of 12

1...6 7 8910 11 12

中文翻译

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ADCLK944BCPZ-R7 替代型号

型号	品牌	替代类型	描述	数据表
ADCLK944BCPZ-WP	ADI	类似代替	2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK944BCPZ-R2	ADI	类似代替	2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer

与ADCLK944BCPZ-R7相关器件

型号	品牌	获取价格	描述	数据表
ADCLK944BCPZ-WP	ADI	获取价格	2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK946	ADI	获取价格	Six LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK946/PCBZ	ADI	获取价格	Six LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK946BCPZ	ADI	获取价格	Six LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK946BCPZ-REEL7	ADI	获取价格	Six LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948	ADI	获取价格	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948/PCBZ	ADI	获取价格	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948BCPZ	ADI	获取价格	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948BCPZ-REEL7	ADI	获取价格	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK950	ADI	获取价格	Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer

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