ADCLK944BCPZ-R7

更新时间： 2024-01-21 16:16:14

品牌	Logo	应用领域
亚德诺 - ADI		时钟驱动器逻辑集成电路 PC
页数	文件大小	规格书
12页	217K
描述
2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer

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技术参数
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ADCLK944BCPZ-R7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	16
Reach Compliance Code：	unknown	风险等级：	5.74
Is Samacsys：	N	系列：	2400
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-PQCC-N16
JESD-609代码：	e3	长度：	3 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	湿度敏感等级：	NOT APPLICABLE
功能数量：	1	反相输出次数：
端子数量：	16	实输出次数：	4
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	0.13 ns
认证状态：	COMMERCIAL	Same Edge Skew-Max（tskwd）：	0.015 ns
座面最大高度：	0.8 mm	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	3 mm	最小 fmax：	6200 MHz
Base Number Matches：	1

ADCLK944BCPZ-R7 数据手册

ADCLK944

If the return is floated, the device exhibits a 100 ꢁ cross-termi-

nation, but the source must then control the common-mode

voltage and supply the input bias currents.

PCB LAYOUT CONSIDERATIONS

The ADCLK944 buffer is designed for very high speed applica-

tions. Consequently, high speed design techniques must be used

to achieve the specified performance. It is critically important to

use low impedance supply planes for both the negative supply

(V_EE) and the positive supply (V_CC) planes as part of a multilayer

board. Providing the lowest inductance return path for switching

currents ensures the best possible performance in the target

application.

ESD/clamp diodes between the input pins prevent the application

from developing excessive offsets to the input transistors. ESD

diodes are not optimized for best ac performance. When a clamp

is required, it is recommended that appropriate external diodes

be used.

Exposed Metal Paddle

The following references to the ground plane assume that the V_EE

power plane is grounded for LVPECL operation. Note that, for

ECL operation, the V_CCpower plane becomes the ground plane.

The exposed metal paddle on the ADCLK944 package is both an

electrical connection and a thermal enhancement. For the device

to function properly, the paddle must be properly attached to

the V_EEpins.

It is also important to adequately bypass the input and output

supplies. Place a 1 μF electrolytic bypass capacitor within several

inches of each V_CCpower supply pin to the ground plane. In

addition, place multiple high quality 0.001 ꢀF bypass capacitors

as close as possible to each V_CCsupply pin, and connect the

capacitors to the ground plane with redundant vias. Select high

frequency bypass capacitors for minimum inductance and ESR.

To improve the effectiveness of the bypass at high frequencies,

minimize parasitic layout inductance. Also, avoid discontinuities

along input and output transmission lines; such discontinuities

can affect jitter performance.

When properly mounted, the ADCLK944 also dissipates heat

through its exposed paddle. The PCB acts as a heat sink for the

ADCLK944. The PCB attachment must provide a good thermal

path to a larger heat dissipation area. This requires a grid of vias

from the top layer of the PCB down to the V_EEpower plane (see

Figure 17). The ADCLK944 evaluation board (ADCLK944/PCBZ)

provides an example of how to attach the part to the PCB.

In a 50 Ω environment, input and output matching have a signif-

icant impact on performance. The buffer provides internal 50 Ω

VIAS TO V POWER

CLK

termination resistors for both the CLK and

inputs. Normally,

PLANE

the return side is connected to the reference pin that is provided.

Bypass the termination potential using ceramic capacitors to

prevent undesired aberrations on the input signal due to parasitic

inductance in the termination return path. If the inputs are dc-

coupled to a source, take care to ensure that the pins are within

the rated input differential and common-mode voltage ranges.

Figure 17. PCB Land for Attaching Exposed Paddle

Rev. 0 | Page 10 of 12

1...7 8 91011 12

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ADCLK944BCPZ-R7 替代型号

型号	品牌	替代类型	描述	数据表
ADCLK944BCPZ-WP	ADI	类似代替	2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK944BCPZ-R2	ADI	类似代替	2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer

与ADCLK944BCPZ-R7相关器件

型号	品牌	获取价格	描述	数据表
ADCLK944BCPZ-WP	ADI	获取价格	2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK946	ADI	获取价格	Six LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK946/PCBZ	ADI	获取价格	Six LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK946BCPZ	ADI	获取价格	Six LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK946BCPZ-REEL7	ADI	获取价格	Six LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948	ADI	获取价格	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948/PCBZ	ADI	获取价格	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948BCPZ	ADI	获取价格	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948BCPZ-REEL7	ADI	获取价格	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK950	ADI	获取价格	Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer

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ADCLK944BCPZ-R7

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