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ADCLK925_15 PDF预览

ADCLK925_15

更新时间: 2022-02-26 11:56:12
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 1104K
描述
Ultrafast SiGe ECL Clock/Data Buffers

ADCLK925_15 数据手册

 浏览型号ADCLK925_15的Datasheet PDF文件第1页浏览型号ADCLK925_15的Datasheet PDF文件第2页浏览型号ADCLK925_15的Datasheet PDF文件第3页浏览型号ADCLK925_15的Datasheet PDF文件第5页浏览型号ADCLK925_15的Datasheet PDF文件第6页浏览型号ADCLK925_15的Datasheet PDF文件第7页 
ADCLK905/ADCLK907/ADCLK925  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
Conditions  
POWER SUPPLY  
Supply Voltage Requirement  
Power Supply Current  
ADCLK905  
VCC − VEE 2.375  
3.63  
V
2.5 V − 5ꢁ to 3.3 V + 10ꢁ  
Static  
Negative Supply Current  
IVEE  
IVCC  
24  
25  
47  
48  
mA  
mA  
mA  
mA  
VCC − VEE = 2.5 V  
40  
63  
VCC − VEE = 3.3 V 10ꢁ  
VCC − VEE = 2.5 V  
Positive Supply Current  
VCC − VEE = 3.3 V 10ꢁ  
ADCLK907  
Negative Supply Current  
IVEE  
IVCC  
48  
50  
94  
96  
mA  
mA  
mA  
mA  
VCC − VEE = 2.5 V  
80  
VCC − VEE = 3.3 V 10ꢁ  
VCC − VEE = 2.5 V  
Positive Supply Current  
126  
VCC − VEE = 3.3 V 10ꢁ  
ADCLK925  
Negative Supply Current  
IVEE  
IVCC  
29  
31  
76  
77  
3
mA  
mA  
mA  
mA  
ps/V  
dB  
VCC − VEE = 2.5 V  
51  
97  
VCC − VEE = 3.3 V 10ꢁ  
VCC − VEE = 2.5 V  
Positive Supply Current  
VCC − VEE = 3.3 V 10ꢁ  
VCC − VEE = 3.0 V 20ꢁ  
VCC − VEE = 3.0 V 20ꢁ  
Power Supply Rejection1  
Output Swing Supply Rejection2  
PSRVCC  
PSRVCC  
26  
1 Change in TPD per change in VCC  
2 Change in output swing per change in VCC  
.
.
Rev. 0 | Page 4 of 16  
 

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