Datasheet > ADCLK907BCPZ-WP

ADCLK907BCPZ-WP

更新时间： 2022-02-26 10:09:53

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	867K
描述
Ultrafast SiGe ECL Clock/Data Buffers

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ADCLK907BCPZ-WP 数据手册

Data Sheet

ADCLK905/ADCLK907/ADCLK925

TYPICAL APPLICATION CIRCUITS

REF

CONNECT V TO V

REF

NOTES

1. PLACING A BYPASS CAPACITOR

FROM V TO GROUND CAN IMPROVE

THE NOISE PERFORMANCE.

Figure 26. Interfacing to CML Inputs

Figure 28. AC Coupling Differential Signals

REF

– 2V

CONNECT V TO V − 2V.

CONNECT V , V

, AND D. PLACE A BYPASS

CAPACITOR FROM V TO GROUND.

REF

ALTERNATIVELY, V , V

, AND D CAN BE

REF

CONNECTED, GIVING A CLEANER LAYOUT AND

A 180º PHASE SHIFT.

Figure 27. Interfacing to PECL

Figure 29. Interfacing to AC-Coupled Single-Ended Inputs

Rev. B | Page 13 of 16

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型号	品牌	描述	获取价格	数据表
ADCLK914	ADI	超快型SiGe开集HVDS时钟/数据缓冲器	获取价格
ADCLK914/PCBZ1	ADI	Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer	获取价格
ADCLK914BCPZ-R2	ADI	Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer	获取价格
ADCLK914BCPZ-R7	ADI	Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer	获取价格
ADCLK914BCPZ-WP	ADI	Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer	获取价格
ADCLK925	ADI	Ultrafast SiGe ECL Clock/Data Buffers	获取价格