ADC12V170HFEB

更新时间： 2024-11-05 04:48:51

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器
页数	文件大小	规格书
22页	562K
描述
12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs

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ADC12V170HFEB 数据手册

October 2007

ADC12V170

12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with

LVDS Outputs

General Description

Features

The ADC12V170 is a high-performance CMOS analog-to-

digital converter with LVDS outputs. It is capable of converting

analog input signals into 12-Bit digital words at rates up to 170

Mega Samples Per Second (MSPS). Data leaves the chip in

a DDR (Dual Data Rate) format; this allows both edges of the

output clock to be utilized while achieving a smaller package

size. This converter uses a differential, pipelined architecture

with digital error correction and an on-chip sample-and-hold

circuit to minimize power consumption and the external com-

ponent count, while providing excellent dynamic perfor-

mance. A unique sample-and-hold stage yields a full-power

bandwidth of 1.1 GHz. The ADC12V170 operates from dual

+3.3V and +1.8V power supplies and consumes 781 mW of

power at 170 MSPS.

1.1 GHz Full Power Bandwidth

■

Internal sample-and-hold circuit

Internal precision 1.0V reference

Single-ended or Differential clock modes

Clock Duty Cycle Stabilizer

Dual +3.3V and +1.8V supply operation

Power-down and Sleep modes

Offset binary or 2's complement output data format

LVDS outputs

■

Pin-compatible: ADC14V155

48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)

■

The separate +1.8V supply for the digital output interface al-

lows lower power operation with reduced noise. A power-

down feature reduces the power consumption to 15 mW while

still allowing fast wake-up time to full operation. In addition

there is a sleep feature which consumes 50 mW of power and

has a faster wake-up time.

Key Specifications

Resolution

12 Bits

■

Conversion Rate

170 MSPS

67.2 dBFS (typ)

85.8 dBFS (typ)

10.9 bits (typ)

1.1 GHz (typ)

781 mW (typ)

SNR (f_IN= 70 MHz)

SFDR (f_IN= 70 MHz)

ENOB (f_IN= 70 MHz)

Full Power Bandwidth

Power Consumption

The differential inputs provide a full scale differential input

swing equal to 2 times the reference voltage. A stable 1.0V

internal voltage reference is provided, or the ADC12V170 can

be operated with an external reference.

Clock mode (differential versus single-ended) and output data

format (offset binary versus 2's complement) are pin-se-

lectable. A duty cycle stabilizer maintains performance over

a wide range of input clock duty cycles.

Applications

High IF Sampling Receivers

■

Wireless Base Station Receivers

Power Amplifier Linearization

The ADC12V170 is pin-compatible with the ADC14V155. It is

available in a 48-lead LLP package and operates over the

industrial temperature range of −40°C to +85°C.

Multi-carrier, Multi-mode Receivers

Test and Measurement Equipment

Communications Instrumentation

Radar Systems

■

Block Diagram

30016802

300168

www.national.com

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与ADC12V170HFEB相关器件

型号	品牌	获取价格	描述	数据表
ADC12V170LFEB	NSC	获取价格	12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs
ADC12XJ1600-Q1	TI	获取价格	ADC12xJ1600-Q1 Quad/Dual/Single Channel, 1.6-GSPS, 12-bit, Analog-to-Digital Converter (AD
ADC12XJ800	TI	获取价格	ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC)
ADC12XJ800-Q1	TI	获取价格	ADC12xJ1600-Q1 Quad/Dual/Single Channel, 1.6-GSPS, 12-bit, Analog-to-Digital Converter (AD
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