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ADC08B3000 PDF预览

ADC08B3000

更新时间: 2024-11-30 03:11:19
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
32页 820K
描述
High Performance, Low Power, 8-Bit, 3 GSPS A/D Converter with 4K Buffer

ADC08B3000 数据手册

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ADVANCE INFORMATION  
June 2006  
ADC08B3000  
High Performance, Low Power, 8-Bit, 3 GSPS A/D  
Converter with 4K Buffer  
General Description  
Features  
n Internal Sample-and-Hold  
Note: This product is currently in development. - ALL  
specifications are design targets and are subject to  
change.  
n Single +1.9V 0.1V Operation  
n Choice of SDR or DDR output clocking  
n Internal selectable 4K Data Buffer  
n Clock Phase Adjust for Multiple ADC Synchronization  
n Guaranteed No Missing Codes  
n Serial Interface for Extended Control  
n Fine Adjustment of Input Full-Scale Range and Offset  
n Duty Cycle Corrected Sample Clock  
The ADC08B3000 is a single, low power, high performance  
CMOS analog-to-digital converter that digitizes signals to 8  
bits resolution at sampling rates up to 3.4 GSPS. Consuming  
a typical 1.8 Watts at 3 GSPS from a single 1.9 Volt supply,  
this device is guaranteed to have no missing codes over the  
full operating temperature range. The unique folding and  
interpolating architecture, the fully differential comparator  
design, the innovative design of the internal sample-and-  
hold amplifier and the self-calibration scheme enable a very  
flat response of all dynamic parameters upto Nyquist, pro-  
ducing a high 7.0 ENOB with a 748 MHz input signal and a  
3 GHz sample rate while providing a 10-18 B.E.R. 3 GSPS is  
achieved through using a 1.5GHz clock. Output formatting is  
offset binary. The device contains a 4K FIFO Capture Buffer  
which is used to feed two 8 bit CMOS output busses at a rate  
up to 200MHz.  
Key Specifications  
n Resolution  
8 Bits  
n Max Conversion Rate  
n Bit Error Rate  
3 GSPS (min)  
10-18 (typ)  
7.0 Bits (typ)  
44 dB (typ)  
TBD  
@
n ENOB 748 MHz Input  
@
n SNR 748 MHz  
n Full Power Bandwidth  
n Power Consumption  
— Operating  
The converter typically consumes less than 20 mW in the  
Power Down Mode and is available in a 128-lead, thermally  
enhanced exposed pad LQFP and operates over the Indus-  
trial (-40˚C TA +85˚C) temperature range.  
1.8 W (typ)  
20 mW (typ)  
— Power Down Mode  
Applications  
n Ranging Applications  
n Test and measurement Applications  
Block Diagram  
20160153  
© 2006 National Semiconductor Corporation  
DS201601  
www.national.com  

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