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ADC08D1000 PDF预览

ADC08D1000

更新时间: 2024-01-23 16:30:26
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
31页 816K
描述
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter

ADC08D1000 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:QFP, QFP120,.87SQ,20针数:128
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.62转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:S-CQFP-G128JESD-609代码:e4
最大线性误差 (EL):0.35%湿度敏感等级:1
模拟输入通道数量:2位数:8
端子数量:128最高工作温度:85 °C
最低工作温度:-40 °C输出位码:OFFSET BINARY
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QFP
封装等效代码:QFP120,.87SQ,20封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):260
电源:1.9 V认证状态:Not Qualified
子类别:Analog to Digital Converters标称供电电压:1.9 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Gold (Ni/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

ADC08D1000 数据手册

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ADVANCE INFORMATION  
September 2004  
ADC08D1000  
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D  
Converter  
General Description  
Features  
n Internal Sample-and-Hold  
NOTE: This product is currently in development. – ALL  
specifications are design targets and are subject to  
change.  
n Single +1.9V 0.1V Operation  
n Choice of SDR or DDR output clocking  
n Interleave Mode for 2x Sampling Rate  
n Multiple ADC Synchronization Capability  
n Guaranteed No Missing Codes  
n Serial Interface for Extended Control  
n Fine Adjustment of Input Full-Scale Range and Offset  
The ADC08D1000 is a dual, low power, high performance  
CMOS analog-to-digital converter that digitizes signals to 8  
bits resolution at sampling rates up to 1.6 GSPS. Consuming  
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,  
this device is guaranteed to have no missing codes over the  
full operating temperature range. The unique folding and  
interpolating architecture, the fully differential comparator  
design, the innovative design of the internal sample-and-  
hold amplifier and the self-calibration scheme enable a very  
flat response of all dynamic parameters beyond Nyquist,  
producing a high 7.5 ENOB with a 500 MHz input signal and  
a 1 GHz sample rate while providing a 10-18 B.E.R. Output  
formatting is offset binary and the LVDS digital outputs are  
compliant with IEEE 1596.3-1996, with the exception of a  
reduced common mode voltage of 0.8V.  
Key Specifications  
n Resolution  
8 Bits  
1 GSPS (min)  
10-18 (typ)  
7.5 Bits (typ)  
0.25 LSB (typ)  
n Max Conversion Rate  
n Bit Error Rate  
@
n ENOB 500 MHz Input  
n DNL  
n Power Consumption  
— Operating  
1.6 W (typ)  
20 mW (typ)  
Each converter has a 1:2 demultiplexer that feeds two LVDS  
buses and reduces the output data rate on each bus to half  
the sampling rate. The two converters can be interleaved  
and used as a single 2 GSPS ADC.  
— Power Down Mode  
Applications  
n Direct RF Down Conversion  
n Digital Oscilloscopes  
n Satellite Set-top boxes  
n Communications Systems  
n Test Instrumentation  
The converter typically consumes less than 20 mW in the  
Power Down Mode and is available in a 128-lead, thermally  
enhanced exposed pad LQFP and operates over the indus-  
trial (-40˚C TA +85˚C) temperature range.  
Block Diagram  
20097453  
© 2004 National Semiconductor Corporation  
DS200974  
www.national.com  

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