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ADC08D1500DEV PDF预览

ADC08D1500DEV

更新时间: 2024-12-01 06:36:19
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
40页 1258K
描述
High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter

ADC08D1500DEV 数据手册

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April 20, 2009  
ADC08D1500  
High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D  
Converter  
Choice of SDR or DDR output clocking  
General Description  
Interleave Mode for 2x Sample Rate  
The ADC08D1500 is a dual, low power, high performance  
Multiple ADC Synchronization Capability  
CMOS analog-to-digital converter that digitizes signals to 8  
bits resolution at sample rates up to 1.7 GSPS. Consuming a  
typical 1.8 Watts at 1.5 GSPS from a single 1.9 Volt supply,  
this device is guaranteed to have no missing codes over the  
full operating temperature range. The unique folding and in-  
terpolating architecture, the fully differential comparator de-  
sign, the innovative design of the internal sample-and-hold  
amplifier and the self-calibration scheme enable a very flat  
response of all dynamic parameters beyond Nyquist, produc-  
ing a high 7.25 ENOB with a 748 MHz input signal and a 1.5  
GHz sample rate while providing a 10-18 C.E.R. Output for-  
matting is binary and the LVDS digital outputs are compatible  
with IEEE 1596.3-1996, with the exception of an adjustable  
common mode voltage between 0.8V and 1.2V.  
Guaranteed No Missing Codes  
Serial Interface for Extended Control  
Fine Adjustment of Input Full-Scale Range and Offset  
Duty Cycle Corrected Sample Clock  
Key Specifications  
Resolution  
8 Bits  
1.5 GSPS (min)  
10-18 (typ)  
7.25 Bits (typ)  
±0.15 LSB (typ)  
Max Conversion Rate  
Error Rate  
ENOB @ 748 MHz Input  
DNL  
Power Consumption  
Each converter has a 1:2 demultiplexer that feeds two LVDS  
buses and reduces the output data rate on each bus to half  
the sample rate. The two converters can be interleaved and  
used as a single 3 GSPS ADC.  
Operating  
Power Down Mode  
1.8 W (typ)  
3.5 mW (typ)  
Applications  
The converter typically consumes less than 3.5 mW in the  
Power Down Mode and is available in a 128-lead, thermally  
enhanced exposed pad LQFP and operates over the Indus-  
trial (-40°C TA +85°C) temperature range.  
Direct RF Down Conversion  
Digital Oscilloscopes  
Satellite Set-top boxes  
Communications Systems  
Features  
Test Instrumentation  
Internal Sample-and-Hold  
Single +1.9V ±0.1V Operation  
Block Diagram  
20152153  
© 2009 National Semiconductor Corporation  
201521  
www.national.com  

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