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ADC08D1500EVAL PDF预览

ADC08D1500EVAL

更新时间: 2024-11-30 21:54:15
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
33页 861K
描述
High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter

ADC08D1500EVAL 数据手册

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PRELIMINARY  
June 2005  
ADC08D1500  
High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D  
Converter  
General Description  
Features  
n Internal Sample-and-Hold  
Note: This product is currently in development. - ALL  
specifications are design targets and are subject to  
change.  
n Single +1.9V 0.1V Operation  
n Choice of SDR or DDR output clocking  
n Interleave Mode for 2x Sampling Rate  
n Multiple ADC Synchronization Capability  
n Guaranteed No Missing Codes  
n Serial Interface for Extended Control  
n Fine Adjustment of Input Full-Scale Range and Offset  
n Duty Cycle Corrected Sample Clock  
The ADC08D1500 is a dual, low power, high performance  
CMOS analog-to-digital converter that digitizes signals to 8  
bits resolution at sampling rates up to 1.7 GSPS. Consuming  
a typical 1.9 Watts at 1.5 GSPS from a single 1.9 Volt supply,  
this device is guaranteed to have no missing codes over the  
full operating temperature range. The unique folding and  
interpolating architecture, the fully differential comparator  
design, the innovative design of the internal sample-and-  
hold amplifier and the self-calibration scheme enable a very  
flat response of all dynamic parameters beyond Nyquist,  
producing a high 7.25 ENOB with a 748 MHz input signal  
and a 1.5 GHz sample rate while providing a 10-18 B.E.R.  
Output formatting is offset binary and the LVDS digital out-  
puts are compliant with IEEE 1596.3-1996, with the excep-  
tion of an adjustable common mode voltage between 0.8V  
and 1.2V.  
Key Specifications  
n Resolution  
8 Bits  
1.5 GSPS (min)  
10-18 (typ)  
7.25 Bits (typ)  
0.15 LSB (typ)  
n Max Conversion Rate  
n Bit Error Rate  
@
n ENOB 748 MHz Input  
n DNL  
n Power Consumption  
— Operating  
1.9 W (typ)  
3.5 mW (typ)  
Each converter has a 1:2 demultiplexer that feeds two LVDS  
buses and reduces the output data rate on each bus to half  
the sampling rate. The two converters can be interleaved  
and used as a single 3 GSPS ADC.  
— Power Down Mode  
Applications  
n Direct RF Down Conversion  
n Digital Oscilloscopes  
n Satellite Set-top boxes  
n Communications Systems  
n Test Instrumentation  
The converter typically consumes less than 3.5 mW in the  
Power Down Mode and is available in a 128-lead, thermally  
enhanced exposed pad LQFP and operates over the Indus-  
trial (-40˚C TA +85˚C) temperature range.  
Block Diagram  
20152153  
© 2005 National Semiconductor Corporation  
DS201521  
www.national.com  

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