Datasheet > ADC08D500

ADC08D500

更新时间： 2024-02-08 18:23:45

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
33页	870K
描述
High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

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技术参数
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ADC08D500 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	HLFQFP,	针数：	128
Reach Compliance Code：	unknown	风险等级：	5.83
最大模拟输入电压：	1.31 V	最小模拟输入电压：	1.21 V
最长转换时间：	0.002 µs	转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	S-PQFP-G128	JESD-609代码：	e0
长度：	20 mm	最大线性误差 (EL)：	0.3516%
湿度敏感等级：	3	模拟输入通道数量：	1
位数：	8	功能数量：	2
端子数量：	128	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出位码：	OFFSET BINARY
输出格式：	PARALLEL, 8 BITS	封装主体材料：	PLASTIC/EPOXY
封装代码：	HLFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
采样速率：	500 MHz	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	1.6 mm	标称供电电压：	1.9 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	20 mm	Base Number Matches：	1

ADC08D500 数据手册

May 2005

ADC08D500

High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D

Converter

General Description

Features

n Internal Sample-and-Hold

The ADC08D500 is a dual, low power, high performance

CMOS analog-to-digital converter that digitizes signals to 8

bits resolution at sampling rates up to 800 MSPS. Consum-

ing a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt

supply, this device is guaranteed to have no missing codes

over the full operating temperature range. The unique folding

and interpolating architecture, the fully differential compara-

tor design, the innovative design of the internal sample-and-

hold amplifier and the self-calibration scheme enable a very

flat response of all dynamic parameters beyond Nyquist,

producing a high 7.5 ENOB with a 250 MHz input signal and

a 500 MHz sample rate while providing a 10^-18B.E.R. Output

formatting is offset binary and the LVDS digital outputs are

compliant with IEEE 1596.3-1996, with the exception of an

adjustable common mode voltage between 0.8V and 1.2V.

n Single +1.9V 0.1V Operation

n Choice of SDR or DDR output clocking

n Interleave Mode for 2x Sampling Rate

n Multiple ADC Synchronization Capability

n Guaranteed No Missing Codes

n Serial Interface for Extended Control

n Fine Adjustment of Input Full-Scale Range and Offset

n Duty Cycle Corrected Sample Clock

Key Specifications

n Resolution

8 Bits

500 MSPS (min)

10^-18(typ)

7.5 Bits (typ)

0.15 LSB (typ)

n Max Conversion Rate

n Bit Error Rate

Each converter has a 1:2 demultiplexer that feeds two LVDS

buses and reduces the output data rate on each bus to half

the sampling rate. The two converters can be interleaved

and used as a single 1 GSPS ADC.

n ENOB 250 MHz Input

n DNL

n Power Consumption

— Operating

1.4 W (typ)

3.5 mW (typ)

The converter typically consumes less than 3.5 mW in the

Power Down Mode and is available in a 128-lead, thermally

enhanced exposed pad LQFP and operates over the Indus-

trial (-40˚C ≤ T_A≤ +85˚C) temperature range.

— Power Down Mode

Applications

n Direct RF Down Conversion

n Digital Oscilloscopes

n Satellite Set-top boxes

n Communications Systems

n Test Instrumentation

Block Diagram

20121453

DS201214

www.national.com

12 3 4 5 6 7...33

中文翻译

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与ADC08D500相关器件

型号	品牌	获取价格	描述	数据表
ADC08D500_08	NSC	获取价格	High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
ADC08D500_09	NSC	获取价格	High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
ADC08D500CIYB	NSC	获取价格	High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
ADC08D500CIYB	ADI	获取价格	High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
ADC08D500CIYB/NOPB	TI	获取价格	8 位、双路 500MSPS 或单路 1.0GSPS 模数转换器 (ADC) \| NNB
ADC08D500DEV	NSC	获取价格	High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
ADC08D500EVAL	NSC	获取价格	High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
ADC08D500EVAL	ADI	获取价格	High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
ADC08D502	TI	获取价格	ADC08D502 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
ADC08D502CIYB	TI	获取价格	ADC08D502 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

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