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ADC08D502CIYB/NOPB PDF预览

ADC08D502CIYB/NOPB

更新时间: 2023-06-19 15:34:23
品牌 Logo 应用领域
德州仪器 - TI 转换器模数转换器
页数 文件大小 规格书
43页 877K
描述
双通道、8 位、500MSPS 模数转换器 (ADC) | NNB | 128 | -40 to 85

ADC08D502CIYB/NOPB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:HLQFP-128针数:128
Reach Compliance Code:compliantECCN代码:3A991.C.1
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.6最大模拟输入电压:0.95 V
最小模拟输入电压:-0.87 V最长转换时间:0.002 µs
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-PQFP-G128
JESD-609代码:e3长度:20 mm
最大线性误差 (EL):0.3516%湿度敏感等级:3
模拟输入通道数量:2位数:8
功能数量:1端子数量:128
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY输出格式:PARALLEL, 8 BITS
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装等效代码:QFP128,.87SQ,20封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.9 V认证状态:Not Qualified
采样速率:500 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.6 mm子类别:Analog to Digital Converters
最大压摆率:665 mA标称供电电压:1.9 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:20 mmBase Number Matches:1

ADC08D502CIYB/NOPB 数据手册

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ADC08D502  
www.ti.com  
SNOSC85 AUGUST 2012  
ADC08D502 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter  
Check for Samples: ADC08D502  
1
FEATURES  
Duty Cycle Corrected Sample Clock  
2
Internal Sample-and-Hold  
APPLICATIONS  
Single +1.9V ±0.1V Operation  
Direct RF Down Conversion  
Digital Oscilloscopes  
Choice of SDR or DDR output clocking  
Multiple ADC Synchronization Capability  
Guaranteed No Missing Codes  
Serial Interface for Extended Control  
Satellite Set-top boxes  
Communications Systems  
Test Instrumentation  
Fine Adjustment of Input Full-Scale Range and  
Offset  
DESCRIPTION  
The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals  
to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single  
1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range.  
The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of  
the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic  
parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample  
rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible  
with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.  
Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each  
bus to half the sampling rate.  
The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead,  
thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C TA +85°C) temperature  
range.  
Table 1. Key Specifications  
VALUE  
8
UNIT  
Resolution  
Bits  
Max Conversion Rate  
Bit Error Rate  
500  
10-18 (typ)  
MSPS (min)  
ENOB @ 250 MHz Input  
DNL  
7.5  
Bits (typ)  
LSB (typ)  
±0.15  
Power Consumption  
Operating  
1.4  
3.5  
W (typ)  
Power Down  
Mode  
mW (typ)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2012, Texas Instruments Incorporated  

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