Datasheet > AD9882A/PCB

AD9882A/PCB

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		显示器
页数	文件大小	规格书
40页	1484K
描述
Dual Interface for Flat Panel Displays

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中文翻译

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数据手册

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AD9882A/PCB 数据手册

AD9882A

Number

Pin Type

Mnemonic Function

Value

Interface

Both

Data Outputs

RED [7:0]

Outputs of Converter Red, Bit 7 is the MSB

3.3 V CMOS

92–99

2–9

12–19

GREEN [7:0] Outputs of Converter Green, Bit 7 is the MSB

BLUE [7:0]

DATACK

Outputs of Converter Bue, Bit 7 is the MSB

Both

Data Clock Output

Data Output Clock for the Analog and Digital

Interface

Both

Digital Video Data

Inputs

R_X0+

R_X0–

R_X1+

R_X1–

R_X2+

R_X2–

Digital Input Channel 0 True

Digital Input Channel 0 Complement

Digital Input Channel 1 True

Digital Input Channel 1 Complement

Digital Input Channel 2 True

Digital Input Channel 2 Complement

Digital Data Clock True

22–25

Digital

Digital Video Clock

Inputs

R_XC+

R_XC–

Digital Data Clock Complement

Data Enable

Control Bits

RTERM

3.3 V CMOS

CTL [0:3]

R_TERM

DDCSCL

DDCSDA

MCL

MDA

Decoded Control Bits

Sets Internal Termination Resistance

HDCP Slave Serial Port Data Clock

HDCP Slave Serial Port Data I/O

HDCP Master Serial Port Data Clock

HDCP Master Serial Port Data I/O

HDCP

3.3 V CMOS

PIN DESCRIPTIONS OF SHARED PINS BETWEEN

ANALOG AND DIGITAL INTERFACES

DATA OUTPUTS

RED—Data Output, Red Channel

HSOUT—Horizontal Sync Output

GREEN—Data Output, Green Channel

BLUE—Data Output, Blue Channel

A reconstructed and phase-aligned version of the video Hsync.

The polarity of this output can be controlled via a serial bus bit.

In analog interface mode, the placement and duration are

variable. In digital interface mode, the placement and duration

are set by the graphics transmitter.

The main data outputs. Bit 7 is the MSB. These outputs are

shared between the two interfaces and behave in accordance

with the active interface. Refer to the Analog Interface and

Digital Interface sections.

VSOUT—Vertical Sync Output

DATACK—Data Output Clock

The separated Vsync from a composite signal or a direct pass-

through of the Vsync input. The polarity of this output can be

controlled via a serial bus bit. The placement and duration in all

modes is set by the graphics transmitter.

Just like the data outputs, the data clock output is shared

between the two interfaces. It behaves differently depending on

which interface is active. Refer to the DATACK—Data Output

Clock section to determine how this pin behaves. .

SERIAL PORT (2-WIRE)

SDA—Serial Port Data I/O

SCL—Serial Port Data Clock

A0—Serial Port Address Input

For a full description of the 2-wire serial register, refer to the

2-Wire Serial Control Register Detail section.

Rev. 0 | Page 8 of 40

1...5 6 789 10 11...40

中文翻译

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与AD9882A/PCB相关器件

型号	品牌	获取价格	描述	数据表
AD9882AKSTZ-100	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9882AKSTZ-140	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9882KST-100	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9882KST-140	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9882KST-140	ROCHESTER	获取价格	SPECIALTY CONSUMER CIRCUIT, PQFP100, PLASTIC, MS-026BED, LQFP-100
AD9882KSTZ-100	ROCHESTER	获取价格	SPECIALTY CONSUMER CIRCUIT, PQFP100, PLASTIC, MS-026BED, LQFP-100
AD9882KSTZ-140	ROCHESTER	获取价格	SPECIALTY CONSUMER CIRCUIT, PQFP100, PLASTIC, MS-026BED, LQFP-100
AD9883	ADI	获取价格	110 MSPS Analog Interface for Flat Panel Displays
AD9883	ADPOW	获取价格	110 MSPS Analog Interface for Flat Panel Displays
AD9883/PCB	ADI	获取价格	110 MSPS Analog Interface for Flat Panel Displays

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