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AD9883/PCB

更新时间: 2024-11-06 22:13:11
品牌 Logo 应用领域
亚德诺 - ADI 显示器
页数 文件大小 规格书
24页 175K
描述
110 MSPS Analog Interface for Flat Panel Displays

AD9883/PCB 数据手册

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110 MSPS Analog Interface for  
Flat Panel Displays  
a
AD9883  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
110 MSPS Maximum Conversion Rate  
300 MHz Analog Bandwidth  
0.5 V to 1.0 V Analog Input Range  
500 ps p-p PLL Clock Jitter at 110 MSPS  
3.3 V Power Supply  
Full Sync Processing  
Sync Detect for ”Hot Plugging”  
Midscale Clamping  
8
R
A/D  
A/D  
A/D  
R
OUTA  
AIN  
CLAMP  
CLAMP  
CLAMP  
8
8
G
IN  
G
B
A
OUTA  
B
IN  
A
OUTA  
Power-Down Mode  
Low Power: 500 mW Typical  
Composite Sync Applications Require an External Coast  
MIDSCV  
HSYNC  
COAST  
CLAMP  
FILT  
DTACK  
HSOUT  
VSOUT  
SOGOUT  
SYNC  
PROCESSING  
AND CLOCK  
GENERATION  
APPLICATIONS  
RGB Graphics Processing  
LCD Monitors and Projectors  
Plasma Display Panels  
Scan Converters  
Microdisplays  
Digital TV  
REF  
BYPASS  
REF  
SCL  
SDA  
SERIAL REGISTER  
AND  
POWER MANAGEMENT  
AD9883  
A
0
GENERAL DESCRIPTION  
12 MHz to 110 MHz. PLL clock jitter is 500 ps p-p typical at  
110 MSPS. When the COAST signal is presented, the PLL  
maintains its output frequency in the absence of HSYNC. A  
sampling phase adjustment is provided. Data, HSYNC and  
Clock output phase relationships are maintained. The AD9883  
also offers full sync processing for composite sync and sync-on-  
green applications.  
The AD9883 is a complete 8-bit, 110 MSPS monolithic analog  
interface optimized for capturing RGB graphics signals from  
personal computers and workstations. Its 110 MSPS encode  
rate capability and full-power analog bandwidth of 300 MHz  
supports resolutions up to SXGA (1280 × 1024 at 60 Hz).  
The AD9883 includes a 110 MHz triple ADC with internal  
1.25 V reference, a PLL, and programmable gain, offset, and  
clamp control. The user provides only a 3.3 V power supply,  
analog input, and HSYNC and COAST signals. Three-state  
CMOS outputs may be powered from 2.5 V to 3.3 V.  
A clamp signal is generated internally or may be provided by the  
user through the CLAMP input pin. This interface is fully pro-  
grammable via a two-wire serial interface.  
Fabricated in an advanced CMOS process, the AD9883 is  
provided in a space-saving 80-lead LQFP surface mount plastic  
package and is specified over the 0°C to 70°C temperature range.  
The AD9883’s on-chip PLL generates a pixel clock from HSYNC  
and COAST inputs. Pixel clock output frequencies range from  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2001  

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