Datasheet > AD9884AKS-100

AD9884AKS-100

更新时间： 2024-11-08 22:05:35

品牌	Logo	应用领域
亚德诺 - ADI		商用集成电路
页数	文件大小	规格书
24页	189K
描述
100 MSPS/140 MSPS Analog Flat Panel Interface

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数据手册
替代型号

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AD9884AKS-100 数据手册

100 MSPS/140 MSPS

Analog Flat Panel Interface

AD9884A

FEATURES

FUNCTIONAL BLOCK DIAGRAM

140 MSPS Maximum Conversion Rate

500 MHz Analog Bandwidth

0.5 V to 1.0 V Analog Input Range

400 ps p-p PLL Clock Jitter

Power-Down Mode

AD9884A

OUTA

CLAMP

A/D

OUTB

3.3 V Power Supply

2.5 V to 3.3 V Three-State CMOS Outputs

Demultiplexed Output Ports

Data Clock Output Provided

Low Power: 570 mW Typical

Internal PLL Generates CLOCK from HSYNC

Serial Port Interface

OUTA

CLAMP

OUTB

OUTA

OUTB

Fully Programmable

Supports Alternate Pixel Sampling for Higher-

Resolution Applications

HSYNC

COAST

CLAMP

CKINV

CKEXT

DATACK

HSOUT

CLOCK

GENERATOR

0.15V

APPLICATIONS

REF

CONTROL

REFIN

RGB Graphics Processing

LCD Monitors and Projectors

Plasma Display Panels

Scan Converters

SDA SCL

PWRDN REFOUT

SOGIN SOGOUT

FILT

GENERAL DESCRIPTION

The AD9884A is a complete 8-bit 140 MSPS monolithic analog

interface optimized for capturing RGB graphics signals from

personal computers and workstations. Its 140 MSPS encode

rate capability and full-power analog bandwidth of 500 MHz

supports display resolutions of up to 1280 × 1024 (SXGA) at

75 Hz with sufficient input bandwidth to accurately acquire and

digitize each pixel.

20 MHz to 140 MHz. PLL clock jitter is typically 400 ps p-p

relative to the input reference. When the COAST signal is pre-

sented, the PLL maintains its output frequency in the absence

of HSYNC. A 32-step sampling phase adjustment is provided.

Data, HSYNC and Data Clock output phase relationships are

always maintained. The PLL can be disabled and an external

clock input provided as the pixel clock.

To minimize system cost and power dissipation, the AD9884A

includes an internal +1.25 V reference, PLL to generate a pixel

clock from HSYNC, and programmable gain, offset and clamp

circuits. The user provides only a +3.3 V power supply, analog

input, and HSYNC signals. Three-state CMOS outputs may be

A clamp signal is generated internally or may be provided by the

user through the CLAMP input pin. This device is fully program-

mable via a two-wire serial port.

Fabricated in an advanced CMOS process, the AD9884A is

provided in a space-saving 128-lead MQFP surface mount plas-

tic package and is specified over a 0°C to +70°C temperature

range.

The AD9884A’s on-chip PLL generates a pixel clock from the

HSYNC input. Pixel clock output frequencies range from

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

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AD9884AKS-100 替代型号

型号	品牌	替代类型	描述	数据表
AD9884KS-100	ADI	功能相似	IC SPECIALTY CONSUMER CIRCUIT, PQFP128, PLASTIC, MQFP-128, Consumer IC:Other

与AD9884AKS-100相关器件

型号	品牌	获取价格	描述	数据表
AD9884AKS-140	ADI	获取价格	100 MSPS/140 MSPS Analog Flat Panel Interface
AD9884AKSZ-100	ROCHESTER	获取价格	SPECIALTY CONSUMER CIRCUIT, PQFP128, PLASTIC, MQFP-128
AD9884AKSZ-140	ADI	获取价格	100 MSPS/140 MSPS Analog Flat Panel Interface
AD9884AKSZ-140	ROCHESTER	获取价格	SPECIALTY CONSUMER CIRCUIT, PQFP128, PLASTIC, MQFP-128
AD9884KS	ADI	获取价格	IC SPECIALTY CONSUMER CIRCUIT, PQFP128, PLASTIC, MQFP-128, Consumer IC:Other
AD9884KS-100	ADI	获取价格	IC SPECIALTY CONSUMER CIRCUIT, PQFP128, PLASTIC, MQFP-128, Consumer IC:Other
AD9886	ADI	获取价格	Analog Interface for Flat Panel Displays
AD9886/PCB	ADI	获取价格	Analog Interface for Flat Panel Displays
AD9886KS-100	ADI	获取价格	Analog Interface for Flat Panel Displays
AD9886KS-140	ADI	获取价格	Analog Interface for Flat Panel Displays

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