AD9886KS-140

更新时间： 2024-09-22 22:20:47

品牌	Logo	应用领域
亚德诺 - ADI		显示器商用集成电路
页数	文件大小	规格书
32页	247K
描述
Analog Interface for Flat Panel Displays

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中文翻译

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数据手册

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AD9886KS-140 数据手册

Analog Interface for

Flat Panel Displays

AD9886

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Analog Interface

140 MSPS Maximum Conversion Rate

330 MHz Analog Bandwidth

0.5 V to 1.0 V Analog Input Range

500 ps p-p PLL Clock Jitter at 140 MSPS

3.3 V Power Supply

ANALOG INTERFACE

CLAMP

AD9886

OUTA

A/D

OUTB

Full Sync Processing

Midscale Clamp for YUV Applications

OUTA

CLAMP

OUTB

OUTA

GENERAL DESCRIPTION

OUTB

The AD9886 is a complete 8-bit 140 MSPS monolithic analog

interface optimized for capturing RGB graphics signals from

personal computers and workstations. Its 140 MSPS encode

rate capability and full-power analog bandwidth of 330 MHz

supports resolutions up to SXGA (1280 × 1024 at 75 Hz).

DATACK

HSYNC

COAST

CLAMP

CKINV

CKEXT

FILT

HSOUT

VSOUT

SYNC

PROCESSING

AND CLOCK

GENERATION

For ease of design and to minimize cost, the AD9886 is a fully

integrated interface solution for FPDs. The AD9886 includes a

140 MHz triple ADC with internal 1.25 V reference, PLL to

generate a pixel clock from an HSYNC, and programmable

gain, offset, and clamp control. The user provides only a 3.3 V

power supply, analog input, and an HSYNC signal. Three-state

CMOS outputs may be powered from 2.5 V to 3.3 V.

SOGOUT

REFOUT

REFIN

REF

SCL

SDA

SERIAL REGISTER AND

POWER MANAGEMENT

The AD9886’s on-chip PLL generates a pixel clock from an

HSYNC. Pixel clock output frequencies range from 12 MHz to

140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.

When the COAST signal is presented, the PLL maintains its

output frequency in the absence of HSYNC. A sampling phase

adjustment is provided. Data, HSYNC and Clock output phase

relationships are maintained. The PLL can be disabled and an

external clock input provided as the pixel clock. The AD9886

also offers full sync processing for composite sync and sync-on-

green applications.

A clamp signal is generated internally or may be provided by the

user through the CLAMP input pin. This interface is fully pro-

grammable via a 2-wire serial interface.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

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与AD9886KS-140相关器件

型号	品牌	获取价格	描述	数据表
AD9887	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9887/PCB	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9887A	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9887AKS-100	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9887AKS-100	ROCHESTER	获取价格	SPECIALTY CONSUMER CIRCUIT, PQFP160, PLASTIC, MS-022DD-1, MQFP-160
AD9887AKS-140	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9887AKS-140	ROCHESTER	获取价格	SPECIALTY CONSUMER CIRCUIT, PQFP160, PLASTIC, MS-022DD-1, MQFP-160
AD9887AKS-170	ADI	获取价格	Dual Interface for Flat Panel Displays
AD9887AKS-170	ROCHESTER	获取价格	Consumer Circuit,
AD9887AKSZ100	ADI	获取价格	IC SPECIALTY CONSUMER CIRCUIT, PQFP160, LEAD FREE, PLASTIC, MS-022DD-1, MQFP-160, Consumer

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