Dual Interface for
Flat Panel Displays
AD9882
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Analog Interface
140 MSPS Maximum Conversion Rate
Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamping
4:2:2 Output Format Mode
AD9882
ANALOG INTERFACE
REF
R
REFBYPASS
8
8
8
OUT
CLAMP
A/D
A/D
A/D
R
AIN
G
OUT
CLAMP
CLAMP
G
AIN
B
OUT
B
AIN
Digital Interface
8
8
8
DVI 1.0 Compatible Interface
112 MHz Operation
High Skew Tolerance of 1 Full Input Clock
Sync Detect for “Hot Plugging”
Supports High Bandwidth Digital Content Protection
DATACK
HSOUT
R
OUT
SOGIN
HSYNC
FILT
SYNC
PROCESSING AND
CLOCK
VSOUT
G
OUT
GENERATION
SOGOUT
VSYNC
B
OUT
SCL
SDA
APPLICATIONS
DATACK
HSOUT
VSOUT
SOGOUT
DE
SERIAL REGISTER AND
POWER MANAGEMENT
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converter
Microdisplays
Digital TV
MUXES
A
0
DIGITAL INTERFACE
8
R
X0+
R
OUT
R
X0–
R
X1+
DVI
RECEIVER
G
8
8
OUT
R
X1–
B
R
OUT
X2+
R
X2–
DATACK
DE
R
XC+
R
GENERAL DESCRIPTION
XC–
R
TERM
DDCSCL
DDCSDA
MCL
The AD9882 offers designers the flexibility of an analog interface
and Digital Visual Interface (DVI) receiver integrated on a single
chip. Also included is support for High bandwidth Digital
Content Protection (HDCP).
HSYNC
VSYNC
HDCP
MDA
Analog Interface
The AD9882 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 ¥ 1024 at 75 Hz).
Digital Interface
The AD9882 contains a DVI 1.0 compatible receiver and supports
display resolutions up to SXGA (1280 ¥ 1024 at 60 Hz). The
receiver features an intra-pair skew tolerance of up to one full
clock cycle.
The analog interface includes a 140 MHz triple ADC with
internal 1.25 V reference, a Phase Locked Loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only a 3.3 V power supply, analog input, and Hsync. Three-
state CMOS outputs may be powered from 2.2 V to 3.3 V.
With the inclusion of HDCP, displays may now receive encrypted
video content. The AD9882 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and renew-
ability of that authentication during transmission as specified by
the HDCP v1.0 protocol.
The AD9882’s on-chip PLL generates a pixel clock from Hsync.
Pixel clock output frequencies range from 12 MHz to 140 MHz.
PLL clock jitter is typically 500 ps p-p at 140 MSPS. The AD9882
also offers full sync processing for composite sync and Sync-on-
Green (SOG) applications.
Fabricated in an advanced CMOS process, the AD9882 is
provided in a space-saving 100-lead LQFP surface-mount plastic
package and is specified over the 0∞C to 70∞C temperature range.
REV. A
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may result from its use. No license is granted by implication or otherwise
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© 2003 Analog Devices, Inc. All rights reserved.