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AD9548BCPZ-REEL7

更新时间： 2024-10-28 06:36:15
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亚德诺 - ADI 晶体时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
112页 1935K
描述
Quad/Octal Input Network Clock Generator/Synchronizer

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AD9548BCPZ-REEL7 数据手册

 浏览型号AD9548BCPZ-REEL7的Datasheet PDF文件第104页浏览型号AD9548BCPZ-REEL7的Datasheet PDF文件第105页浏览型号AD9548BCPZ-REEL7的Datasheet PDF文件第106页浏览型号AD9548BCPZ-REEL7的Datasheet PDF文件第108页浏览型号AD9548BCPZ-REEL7的Datasheet PDF文件第109页浏览型号AD9548BCPZ-REEL7的Datasheet PDF文件第110页 
AD9548  
CALCULATING DIGITAL FILTER COEFFICIENTS  
It can also be shown that the adjusted open-loop bandwidth leads  
to T2 (the secondary time constant of the second order loop filter)  
expressed as  
The digital loop filter coefficients (α, β, γ, and δ (see Figure 40))  
relate to the time constants (T1, T2, and T3) associated with the  
equivalent analog circuit for a third order loop filter (Figure 66).  
FROM  
CHARGE  
PUMP  
1
TO  
VCO  
R3  
T2 =  
2
ωC  
(
T1 + T3  
)
C3  
C1  
Calculation of the digital loop filter coefficients requires a scaling  
constant, K (related to the system clock frequency, fS), and the PLL  
feedback divide ratio, D.  
C2  
Figure 66. Third Order Analog Loop Filter  
30,517,578,125  
K =  
fS  
233  
The design process begins by deciding on two design parameters  
related to the second order loop filter shown in Figure 67: the  
desired open-loop bandwidth (fP) and phase margin (θ).  
U
D = S + +1  
V
where S, U, and V are the integer and fractional feedback divider  
values that reside in the profile registers. Keep in mind that the  
desired integer feedback divide ratio is one more than the stored  
value of S (hence, the +1 term in the equation for D in this  
equation). This leads to the digital filter coefficients given by  
FROM  
TO  
CHARGE  
VCO  
PUMP  
C1  
C2  
2
2
ωC 2T2 D  
T1 K  
(
1+  
(
ωCT1  
)
)(1+  
(
)
ωCT3  
)
)
α =  
Figure 67. Second Order Analog Loop Filter  
2
1+  
(
ωCT2  
An analysis of the second order loop filter leads to its primary  
time constant, T1. It can be shown that T1 is expressible in terms of  
fP and θ as  
⎛
⎞
− 32  
1
1
⎜
⎜
⎟
⎟
β =  
γ =  
δ =  
+
fS T1 T2  
⎝
⎠
1− sin(θ)  
T1 =  
− 32  
fST1  
ωP cos(θ)  
where ωP = 2πfP .  
32  
fST3  
An analysis of the third order loop filter leads to the definition of  
another time constant, T3. It can be shown that T3 is expressible in  
terms of the desired amount of additional attenuation introduced  
by R3 and C3 at some specified frequency offset (fOFFSET) from the  
PLL output frequency.  
Calculation of the coefficient register values requires the  
application of some special functions described as follows:  
The if() function  
y = if(test_statement, true_value, false_value)  
ATTEN  
10  
10  
−1  
where test_statement is a conditional expression (for example, x <  
3), true_value is what y equals if the conditional expression is true,  
and false_value is what y equals if the conditional expression is  
false.  
T3 =  
ωOFFSET  
where  
.
ωOFFSET = 2πfOFFSET  
Note that ATTEN is the desired excess attenuation in decibels.  
Furthermore, ATTEN and ωOFFSET should be chosen so that  
The round() function  
y = round(x)  
1
T3 ≤  
5 fP  
With an expression for T1 and T3, it is possible to define an  
adjusted open-loop bandwidth (fC) that is slightly less than fP. It  
can be shown that ωC (fC expressed as a radian frequency) is  
expressible in terms of T1, T3, and θ (phase margin) as  
2
⎡
⎢
⎤
(
T1 + T3  
)
tan(θ)  
T1T3 +  
(
T1 + T3  
)
⎥
−1  
2
ωC =  
1+  
2
T1T3 +  
(
T1 + T3  
)
[
(
T1 + T3  
)
tan(θ)  
]
⎢
⎣
⎥
⎦
Rev. 0 | Page 107 of 112  
 
 
 
 
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AD9548BCPZ-REEL7 替代型号

型号 品牌 替代类型 描述 数据表
AD9548BCPZ ADI

完全替代

 Quad/Octal Input Network Clock Generator/Synchronizer

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