Data Sheet
AD9207
12-Bit, 6 GSPS, JESD204B/JESD204C Dual ADC
FEATURES
APPLICATIONS
► Flexible reconfigurable common platform design
► Supports single, dual, and quad band per channel
► Datapaths and DSP blocks are fully bypassable
► On-chip PLL with multichip synchronization
► External RFCLK input option for off-chip PLL
► Support clock input frequencies up to 12 GHz
► Maximum ADC sample rate up to 6 GSPS
► Useable analog bandwidth to 8 GHz
► Wireless communications infrastructure
► Microwave point to point, E-band, and 5G mmWave
► Broadband communications systems, satellite communications
► DOCSIS 3.1 and 4.0 CMTS
► Electronic warfare
► Electronic test and measurement systems
GENERAL DESCRIPTION
► Maximum data rate up to 6 GSPS using JESD204C
► Noise density: −153 dBFS/Hz
► ADC AC performance at 6 GSPS, input at 2.7 GHz, −1 dBFS
► Full-scale sine wave input voltage: 1.475 V p-p
► Noise figure: 25.3 dB
► HD2: −70 dBFS
► HD3: −68 dBFS
► Worst other (excluding HD2 and HD3): −84 dBFS
► Versatile digital features
► Selectable decimation filters
The AD9207 is a dual, 12-bit, 6 GSPS analog-to-digital converter
(ADC). The ADC input features an on-chip wideband buffer with
overload protection. This device is designed to support applications
capable of direct sampling wideband signals up to 8 GHz. An on-
chip, low phase noise, phase-locked loop (PLL) clock synthesizer
is available to generate the ADC sampling clock, which simplifies
the printed circuit board (PCB) distribution of a high frequency
clock signal. A clock output buffer is available to transmit the ADC
sampling clock to other devices.
The dual ADC cores have code error rates (CER) better than
2 × 10−15. Low latency fast detection and signal monitoring are
available for automatic gain control (AGC) purposes. A flexible
192-tap programmable finite impulse response filter (PFIR) is avail-
able for digital filtering and/or equalization. Programmable integer
and fractional delay blocks support compensation for analog delay
mismatches.
► Configurable DDC
► 8 fine complex DDCs and 4 coarse complex DDCs
► 48-bit NCO per DDC
► Option to bypass fine and coarse DDC
► Programmable 192-tap PFIR filter for receive equalization
► Supports 4 different profile settings loaded via the GPIOx pins
► Programmable delay per datapath
► Receive AGC support
► Fast detect with low latency for fast AGC control
► Signal monitor for slow AGC control
► Dedicated AGC support pins
The digital signal processing (DSP) block consists of two coarse
digital downconverters (DDCs) and four fine DDCs per ADC pair.
Each ADC can operate with one or two main DDC stages in
support of multiband applications. The four additional fine DDC
stages are available to support up to four bands per ADC. The
48-bit numerically controlled oscillators (NCOs) associated with
each DDC support fast frequency hopping (FFH) while maintaining
synchronization with up to 16 unique frequency assignments select-
ed via the general-purpose input and output (GPIOx) pins or the
serial port interface (SPI).
► Auxiliary features
► Fast frequency hopping
► ADC clock driver with selectable divide ratios
► On-chip temperature monitoring unit
► Flexible GPIOx pins
► SERDES JESD204B/JESD204C interface, 8 lanes up to
24.75 Gbps
The AD9207 supports one or two JTx links that can be configured
for either JESD204B or JESD204C subclass operation, which al-
lows different datapath configurations for each ADC. Multidevice
synchronization is supported through the SYSREF± input pins.
See the Outline Dimensions section and the Ordering Guide section
for more information.
► 8 lanes JESD204B/JESD204C transmitter (JTx)
► JESD204B compliance with the maximum 15.5 Gbps
► JESD204C compliance with the maximum 24.75 Gbps
► Supports real or complex digital data (8 bit, 12 bit, 16 bit, or
24 bit)
► Outline Dimensions
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
5秒后页面跳转
三星深化印度制造布局，供应链本地化进程加速
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
意法半导体发布第四代SiC技术，助力电动汽车电驱
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
