14-Bit, 3 GSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9208
Data Sheet
2 integrated, wideband digital processors per channel
FEATURES
48-bit NCO
4 cascaded half-band filters
Phase coherent NCO switching
Up to 4 channels available
Serial port control
Integer clock with divide by 2 and divide by 4 options
Flexible JESD204B lane configurations
On-chip dither
JESD204B (Subclass 1) coded serial digital outputs
Support for lane rates up to 16 Gbps per lane
1.65 W total power per channel at 3 GSPS (default settings)
Performance at −2 dBFS amplitude, 2.6 GHz input
SFDR = 70 dBFS
SNR = 57.2 dBFS
Performance at −9 dBFS amplitude, 2.6 GHz input
SFDR = 78 dBFS
SNR = 59.5 dBFS
Integrated input buffer
APPLICATIONS
Diversity multiband and multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A
Electronic test and measurement systems
Phased array radar and electronic warfare
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
Noise density = −152 dBFS/Hz
0.975 V, 1.9 V, and 2.5 V dc supply operation
9 GHz analog input full power bandwidth (−3 dB)
Amplitude detect bits for efficient AGC implementation
FUNCTIONAL BLOCK DIAGRAM
AVDD1
(0.975V)
AVDD2
(1.9V)
AVDD3 AVDD1_SR
DVDD
(0.975V)
DRVDD1 DRVDD2 SPIVDD
(2.5V)
(0.975V)
(0.975V)
(1.9V)
(1.9V)
BUFFER
14
VIN+A
VIN–A
ADC
CORE
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SERDOUT4±
SERDOUT5±
SERDOUT6±
SERDOUT7±
DIGITAL DOWN-
CONVERTER
JESD204B
8
LINK
AND
FAST
SIGNAL
DETECT
MONITOR
Tx
DIGITAL DOWN-
CONVERTER
OUTPUTS
14
VIN+B
VIN–B
ADC
CORE
BUFFER
VREF
SYNCINB±
PDWN/STBY
JESD204B
CLOCK
DISTRIBUTION
FD_A/GPIO_A0
SUBCLASS 1
CONTROL
SYSREF±
CLK+
GPIO_A1
GPIO MUX
FD_B/GPIO_B0
GPIO_B1
SPI AND
CONTROL
REGISTERS
CLK–
÷2
÷4
AD9208
AGND
SDIO SCLK CSB
DRGND
DGND
Figure 1.
Rev. 0
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