12-Bit, 6 GSPS/10.25 GSPS, JESD204B,
RF Analog-to-Digital Converter
AD9213
Data Sheet
The AD9213 features a 16-lane JESD204B interface to support
maximum bandwidth capability.
FEATURES
High instantaneous dynamic range
NSD
The AD9213 achieves dynamic range and linearity performance
−155 dBFS/Hz at 10 GSPS with −9 dBFS, 170 MHz input
−153 dBFS/Hz at 10 GSPS with −1 dBFS, 170 MHz input
SFDR: 70 dBFS at 10 GSPS with −1 dBFS, 1000 MHz input
SFDR excluding H2 and H3 (worst other spur): 89 dBFS at
10 GSPS with −1 dBFS, 1000 MHz input
Low power dissipation: <4.6 W typical at 10 GSPS
Integrated input buffer (6.5 GHz input bandwidth)
1.4 V p-p full-scale analog input with RIN = 50 Ω
Overvoltage protection
16-lane JESD204B output (up to 16 Gbps line rate)
Multichip synchronization capable with 1 sample accuracy
DDC NCO synchronization included
Integrated DDC
Selectable decimation factors
while consuming <4.6 W typical. The device is based on an inter-
leaved pipeline architecture and features a proprietary calibration
and randomization technique that suppresses interleaving spurious
artifacts into its noise floor. The linearity performance of the
AD9213 is preserved by a combination of on-chip dithering and
calibration, which results in excellent spurious-free performance
over a wide range of input signal conditions.
Applications that require less instantaneous bandwidth can benefit
from the on-chip, digital signal processing (DSP) capability of
the AD9213 that reduces the output data rate along with the
number of JESD204B lanes required to support the device. The
DSP path includes a digital downconverter (DDC) with a 48-bit,
numerically controlled oscillator (NCO), followed by an I/Q digital
decimator stage that allows selectable decimation rates that are
factors of two or three. For fast frequency hopping applications, the
AD9213 NCO supports up to 16 profile settings with a separate
trigger input, allowing wide surveillance frequency coverage at
a reduced JESD204B lane count.
16 profile settings for fast frequency hopping
Fast overrange detection for efficient AGC
On-chip temperature sensor
On-chip negative voltage generators
Low CER: <1 × 10−16
The AD9213 supports sample accurate multichip synchronization
that includes synchronization of the NCOs. The AD9213 is
offered in a 192-ball ball grid array (BGA) package and is
specified over a junction temperature range of −20°C to +115°C.
12 mm × 12 mm, 192-ball BGA-ED package
GENERAL DESCRIPTION
The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio
frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz
input bandwidth. The AD9213 supports high dynamic range
frequency and time domain applications requiring wide instan-
taneous bandwidth and low conversion error rates (CER).
FUNCTIONAL BLOCK DIAGRAM
AVDD2 AVDD
(2.0V) (1.0V) AGND
DVDD
(1.0V)
JVDD2
(2.0V)
JVDD
(1.0V)
2× DIGITAL
GAIN
AD9213
AVNN1
(–1.0V)
SERDOUTx[0]
SERDOUTx[1]
BUFFER
16
12
VIN_P
VIN_N
ADC
16
I/Q
CORE
DIGITAL
DOWN
CONVERTER
SERDOUTx[15]
DGND
VCM
FD
SIGNAL
MONITOR
SYNCINB_x
SYSREF_x
JESD204B
SUBCLASS 1
CONTROL
CLOCK
DISTRIBUTION
CLK_P
CLK_N
TRIG_x
GPIO
ASSIGNMENT
SPI
CONTROL
SVDD2
(2.0V)
CLKVDD_LF
(1.0V)
GPIO[0] TO GPIO[4] SDIO SCLK CSB
Figure 1.
Rev. A
Document Feedback
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Technical Support
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www.analog.com
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