AD6624A
SOFT_SYNC Control Register
Access Control Register (ACR)
The Access Control Register serves to define the channel or
channels that receive an access from the microport or Serial Port 0.
External Address [5] is the SOFT_SYNC control register and is
write only.
Bit 7 of this register is the autoincrement bit. If this bit is a 1,
the CAR register described below will increment its value after
every access to the channel. This allows blocks of address space
such as Coefficient Memory to be initialized more efficiently.
Bits 0–3 of this register are the SOFT_SYNC control bits. These
pins may be written to by the controller to initiate the synchro-
nization of a selected channel. Although there are four inputs,
these do not necessarily go to the channel of the same number.
This is fully configurable at the channel level as to which bit to
look at. All four channels may be configured to synchronize from a
single position, or they may be paired or all independent.
Bit 6 of the register is the broadcast bit and determines how Bits
5–2 are interpreted. If broadcast is 0, Bits 5–2, which are referred
to as instruction bits (Instruction [3:0]), are compared with the
CHIP_ID [3:0] pins. The instruction that matches the CHIP_ID
[3:0] pins will determine the access. This allows up to 16 chips
to be connected to the same port and memory mapped without
external logic. This also allows the same serial port of a host
processor to configure up to 16 chips. If the broadcast bit is
high, the Instruction [3:0] word allows multiple AD6624A
channels and/or chips to be configured simultaneously, indepen-
dent of the CHIP_ID[3:0] pins. Ten possible instructions are
defined in Table XII. This is useful for smart antenna systems
where multiple channels listening to a single antenna or carrier
can be simultaneously configured. The x(s) in the table represent
“don’t cares” in the digital decoding.
Bit 4 determines if the synchronization is to apply to a chip
start. If this bit is set, a chip start will be initiated.
Bit 5 determines if the synchronization is to apply to a chip hop.
If this bit is set, the NCO frequency will be updated when the
SOFT_SYNC occurs.
Bit 6 configures how the internal data bus is configured. If this
bit is set low, the internal ADC data buses are configured nor-
mally. If this bit is set, the internal test signals are selected. The
internal test signals are configured in Bit 7 of this register.
Bit 7 if set clear, a negative full-scale signal is generated and
made available to the internal data bus. If this bit is high, inter-
nal pseudo-random sequence generator is enabled and this data
is available to the internal data bus. The combined functions of
Bits 6 and 7 facilitate verification of a given filter design. Also,
in conjunction with the MISR registers, allow for detailed in-
system chip testing. In conjunction with the JTAG test board,
very high levels of chip verification can be done during system
test, in both the factory and field.
Table XII. Microport Instructions
Instruction
Comment
0000
0001
0010
0100
1000
All chips and all channels will get the access.
Channel 0, 1, 2 of all chips will get the access.
Channel 1, 2, 3 of all chips will get the access.
All chips will get the access.*
All chips with Chip_ID[3:0] = xxx0 will get
the access.*
PIN_SYNC Control Register
External Address [4] is the PIN_SYNC control register and is
write only.
1001
1100
1101
1110
1111
All chips with Chip_ID[3:0] = xxx1 will get
the access.*
All chips with Chip_ID[3:0] = xx00 will get
the access.*
All chips with Chip_ID[3:0] = xx01 will get
the access.*
All chips with Chip_ID[3:0] = xx10 will get
the access.*
Bits 0–3 of this register are the SYNC_EN control bits. These
pins may be written to by the controller to allow pin synchro-
nization of a selected channel. Although there are four inputs,
these do not necessarily go to the channel of the same number.
This is fully configurable at the channel level as to which bit to
look at. All four channels may be configured to synchronize
from a single position, or they may be paired or all independent.
All chips with Chip_ID[3:0] = xx11 will get
the access.*
Bit 4 determines if the synchronization is to apply to a chip
start. If this bit is set, a chip start will be initiated when the
PIN_SYNC occurs.
*A[9:8] bits control which channel is decoded for the access.
Bit 5 determines if the synchronization is to apply to a chip hop.
If this bit is set, the NCO Frequency will be updated when the
when the PIN_SYNC occurs.
External Memory Map
When broadcast is enabled (Bit 6 set high), readback is not valid
because of the potential for internal bus contention. Therefore,
if readback is subsequently desired, the broadcast bit should
be set low.
Bit 6 is used to ignore repetitive synchronization signals. In
some applications, this signal may occur periodically. If this bit
is clear, each PIN_SYNC will restart/hop the channel. If this bit
is set, only the first occurrence will cause the chip to take action.
Bits 1–0 of this register are address bits that decode which of the
four channels are being accessed. If the Instruction bits decode
an access to multiple channels, these bits are ignored. If the
Instruction decodes an access to a subset of chips, the A[9:8] bits
will otherwise determine the channel being accessed.
Bit 7 is used with Bits 6 and 7 of external address 5. When this
bit is cleared, the data supplied to the internal data bus simulates a
normal ADC. When this bit is set, the data supplied is in the
form of a time-multiplexed ADC such as the AD6600 (this
allows the equivalent of testing in the 4-channel input mode).
Internally, when set, this bit forces the IEN pin to toggle as if it
were driven by the A/B signal of the AD6600.
Channel Address Register (CAR)
This register represents the 8-bit internal address of each channel.
If the autoincrement bit of the ACR is 1, this value will be incre-
mented after every access to the DR0 register, which will in
turn access the location pointed to by this address. The Channel
Address register cannot be read back while the broadcast bit
is set high.
SLEEP Control Register
External Address [3] is the sleep register.
–34–
REV. 0
5秒后页面跳转
LM317T数据手册解读：产品特性、应用、封装与引脚详解
一文带你了解?DB3二极管好坏判断、参数信息、替代推荐
LM358DR数据手册：引脚说明、电气参数及替换型号推荐
OP07CP数据手册解读：引脚信息、电子参数
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
