AD6624AS/PCB

更新时间： 2024-01-24 01:24:58

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
40页	611K
描述
Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)

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技术参数
数据手册

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AD6624AS/PCB 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	128
Reach Compliance Code：	unknown	ECCN代码：	5A991.B.1
HTS代码：	8542.31.00.01	风险等级：	5.82
JESD-30 代码：	R-PQFP-G128	长度：	20 mm
功能数量：	1	端子数量：	128
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	3.4 mm
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

AD6624AS/PCB 数据手册

AD6624A

JTAG BOUNDARY SCAN

SAMPLE/PRELOAD (3’b010) Allows the IC to remain in

normal functional mode and selects the boundary-scan register

to be connected between TDI and TDO. The boundary-scan

the functional data entering and leaving the IC. Also, test

data can be preloaded into the boundary scan register before

an EXTEST instruction.

The AD6624A supports a subset of IEEE Standard 1149.1 specifi-

cations. For additional details of the standard, please see “IEEE

Standard Test Access Port and Boundary-Scan Architecture,”

IEEE-1149 publication from IEEE.

The AD6624A has five pins associated with the JTAG interface.

These pins are used to access the on-chip Test Access Port and

are listed in the table below. All input JTAG pins are pull-up,

except for TCLK which has a pull-down.

HIGHZ (3’b011) Sets all outputs to high impedance state.

Selects the 1-bit bypass register to be connected between

TDI and TDO.

Table XIV. Boundary Scan Test Pins

CLAMP (3’b100) Sets the outputs of the IC to logic levels

determined by the boundary-scan register and selects the 1-bit

bypass register to be connected between TDI and TDO. Before

this instruction, boundary-scan data can be preloaded with

the SAMPLE/PRELOAD instruction.

Name

Pin Number

Description

TRST

TCLK

TMS

TDI

Test Access Port Reset

Test Clock

Test Access Port Mode Select

Test Data Input

Test Data Output

BYPASS (3’b111) Allows the IC to remain in normal functional

mode and selects 1-bit bypass register between TDI and TDO.

During this instruction, serial data is transferred from TDI to

TDO without affecting operation of the IC.

TDO

The AD6624A supports the op codes as shown below. These

instructions set the mode of the JTAG interface.Address 02 is

the dwell time for input channel A. This sets the

INTERNAL WRITE ACCESS

Up to 20 bits of data (as needed) can be written by the process

described below. Any high order bytes that are needed are writ-

ten to the corresponding data registers defined in the external

3-bit address space. The least significant byte is then written to

DR0 at address (000). When a write to DR0 is detected, the

internal microprocessor port state machine then moves the data

in DR2-DR0 to the internal address pointed to by the address in

the LAR and AMR.

Table XV. Boundary Scan Op Codes

Instruction

Op Code

IDCODE

BYPASS

SAMPLE/PRELOAD

EXTEST

HIGHZ

001

111

010

000

011

100

Write Pseudocode

void write_micro(ext_address, int data);

CLAMP

main();

{

The Vendor Identification Code can be accessed through the

IDCODE instruction and has the following format.

/* This code shows the programming of the NCO phase offset

variable address is the External Address A[2:0] and data is the

value to be placed in the external interface register.

Table XVI. Vendor ID Code

MSB

Version

Part

Number

Manufacturing

ID #

LSB

Mandatory

Internal Address = 0x087

0000

0010

0111

1000

1100

000 1110 0101

// holding registers for NCO phase byte wide access data

int d1, d0;

// NCO frequency word (16-bits wide)

NCO_PHASE = 0xCBEF;

A BSDL file for this device is available; please contact Analog

Devices, Inc. for more information.

// write ACR

write_micro(7, 0x03);

EXTEST (3’b000) Places the IC into an external boundary-test

mode and selects the boundary-scan register to be connected

between TDI and TDO. During this, the boundary-scan regis-

ter is accessed to drive test data off-chip via boundary outputs

and receive test data off-chip from boundary inputs.

// write CAR

write_micro(6, 0x03);

// write DR1 with D[15:8]

d1 = (NCO_PHASE & 0xFF00) >> 8;

write_micro(1, d1);

IDCODE (3’b001) Allows the IC to remain in its functional

mode and selects device ID register to be connected between

TDI and TDO. Accessing the ID register does not interfere

with the operation of the IC.

// write DR0 with D[7:0]

// On this write all data is transferred to the internal address

d0 = NCO_FREQ & 0xFF;

write_micro(0, d0);

} // end of main

REV. 0

–37–

1...34 35 363738 39 40

中文翻译

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与AD6624AS/PCB相关器件

型号	品牌	获取价格	描述	数据表
AD6624S/PCB	ADI	获取价格	Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP)
AD6624XS	ADI	获取价格	IC SPECIALTY TELECOM CIRCUIT, PQFP128, METRIC, QFP-128, Telecom IC:Other
AD662AQ	ETC	获取价格	12-Bit Digital-to-Analog Converter
AD662BQ	ETC	获取价格	12-Bit Digital-to-Analog Converter
AD662JN	ETC	获取价格	12-Bit Digital-to-Analog Converter
AD662KN	ETC	获取价格	12-Bit Digital-to-Analog Converter
AD662SQ	ETC	获取价格	12-Bit Digital-to-Analog Converter
AD662TQ	ETC	获取价格	12-Bit Digital-to-Analog Converter
AD6630	ADI	获取价格	Differential, Low Noise IF Gain Block with Output Clamping
AD6630AR	ADI	获取价格	Differential, Low Noise IF Gain Block with Output Clamping

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