Datasheet > AD5342_15

AD5342_15

更新时间： 2022-02-26 12:58:04

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	327K
描述
2.5 V to 5.5 V, 230A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs

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AD5342_15 数据手册

AD5332/AD5333/AD5342/AD5343

AD5343 FUNCTIONAL BLOCK DIAGRAM

AD5343 PIN CONFIGURATION

REF

HBEN

REF

POWER-ON

RESET

OUT

AD5343

HIGH BYTE

OUT

12-BIT

16 DB

GND

AD5343

TOP VIEW

14 DB

(Not to Scale)

DAC

LOW BYTE

12-BIT

DAC

BUFFER

OUT

HBEN

CLR

INTER-

FACE

LOGIC

HIGH BYTE

LDAC

DAC

LOW BYTE

12-BIT

DAC

OUT

RESET

CLR

LDAC

POWER-DOWN

LOGIC

GND

AD5343 PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

Function

HBEN

This pin is used when writing to the device to determine if data is written to the high byte register or the

low byte register.

V_REF

Unbuffered reference input for both DACs.

_OUTA

_OUTB

Output of DAC A. Buffered output with rail-to-rail operation.

Output of DAC B. Buffered output with rail-to-rail operation.

GND

Ground reference point for all circuitry on the part.

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

Address pin for selecting between DAC A and DAC B.

CLR

LDAC

Asynchronous active low control input that clears all input registers and DAC registers to zeros.

Active low control input that updates the DAC registers with the contents of the input registers. This allows

all DAC outputs to be simultaneously updated.

Power-Down Pin. This active low control pin puts all DACs into power-down mode.

Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

V_DD

10 ␮F capacitor in parallel with a 0.1 ␮F capacitor to GND.

13–20

DB₀–DB₇

Eight Parallel Data Inputs. DB₇is the MSB of these eight bits.

–8–

REV. 0

1...5 6 789 10 11...20

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