2.5 V to 5.5 V, Parallel Interface
Octal Voltage Output 8-/10-/12-Bit DACs
AD5346/AD5347/AD5348
GENERAL DESCRIPTION
FEATURES
The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit
DACs, operating from a 2.5 V to 5.5 V supply. These devices
incorporate an on-chip output buffer that can drive the output
to both supply rails, and also allow a choice of buffered or
unbuffered reference input.
AD5346: octal 8-bit DAC
AD5347: octal 10-bit DAC
AD5348: octal 12-bit DAC
Low power operation: 1.4 mA (max) @ 3.6 V
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Guaranteed monotonic by design over all codes
Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
CS
The AD5346/AD5347/AD5348 have a parallel interface.
selects the device and data is loaded into the input registers on
WR
the rising edge of
. A readback feature allows the internal
LDAC
Simultaneous update of DAC outputs via
pin
DAC registers to be read back through the digital port.
CLR
Asynchronous
Readback
facility
The GAIN pin on these devices allows the output range to be
Buffered/unbuffered reference inputs
WR
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C
set at 0 V to VREF or 0 V to 2 × VREF
Input data to the DACs is double-buffered, allowing simultane-
LDAC
.
20 ns
time
ous update of multiple DACs in a system using the
pin.
input is also provided, which resets the
CLR
An asynchronous
APPLICATIONS
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
V
V
AB
V
CD
REF
AGND DGND
DD
REF
POWER-ON
RESET
AD5348
BUF
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
GAIN
BUFFER
V
A
B
OUT
DB11
INPUT
REGISTER
DAC
REGISTER
.
.
.
STRING
DAC B
BUFFER
BUFFER
V
OUT
DB0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
V
C
OUT
INTER-
FACE
LOGIC
CS
DAC
REGISTER
INPUT
REGISTER
STRING
DAC D
V
D
BUFFER
BUFFER
OUT
RD
DAC
REGISTER
INPUT
REGISTER
STRING
DAC E
V
E
F
WR
OUT
DAC
REGISTER
INPUT
REGISTER
STRING
DAC F
V
OUT
A2
A1
A0
BUFFER
BUFFER
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC G
V
V
G
OUT
DAC
REGISTER
INPUT
REGISTER
STRING
DAC H
H
OUT
CLR
POWER-DOWN
LOGIC
LDAC
V
GH
V
EF
REF
PD
REF
Figure 1.
1Protected by U.S. Patent No. 5,969,657; other patents pending.
Rev. 0
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