Datasheet > AD5342_15

AD5342_15

更新时间： 2022-02-26 12:58:04

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	327K
描述
2.5 V to 5.5 V, 230A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs

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AD5342_15 数据手册

AD5332/AD5333/AD5342/AD5343

AD5332 FUNCTIONAL BLOCK DIAGRAM

AD5332 PIN CONFIGURATION

REF

POWER-ON

RESET

AD5332

OUT

8-BIT

DAC

INPUT

8-BIT

DAC

16 DB

GND

BUFFER

OUT

AD5332

TOP VIEW

(Not to Scale)

14 DB

INTER-

FACE

LOGIC

DAC

INPUT

8-BIT

DAC

CLR

BUFFER

LDAC

RESET

POWER-DOWN

LOGIC

CLR

LDAC

GND

REF

AD5332 PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

V_REF

Function

Unbuffered reference input for DAC B.

GND

_REFA

_OUTA

_OUTB

Unbuffered reference input for DAC A.

Output of DAC A. Buffered output with rail-to-rail operation.

Output of DAC B. Buffered output with rail-to-rail operation.

Ground reference point for all circuitry on the part.

Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

Active low Write Input. This is used in conjunction with CS to write data to the parallel interface.

Address pin for selecting which DAC A and DAC B.

CLR

LDAC

Asynchronous active low control input that clears all input registers and DAC registers to zeros.

Active low control input that updates the DAC registers with the contents of the input registers. This

allows all DAC outputs to be simultaneously updated.

Power-Down Pin. This active low control pin puts all DACs into power-down mode.

Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

10 ␮F capacitor in parallel with a 0.1 ␮F capacitor to GND.

V_DD

13–20

DB₀–DB₇

Eight Parallel Data Inputs. DB₇is the MSB of these eight bits.

–5–

REV. 0

1 2 3 456 7 8...20

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