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AD5342_15

更新时间： 2022-02-26 12:58:04
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 327K
描述
2.5 V to 5.5 V, 230A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs

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AD5342_15 数据手册

 浏览型号AD5342_15的Datasheet PDF文件第1页浏览型号AD5342_15的Datasheet PDF文件第2页浏览型号AD5342_15的Datasheet PDF文件第4页浏览型号AD5342_15的Datasheet PDF文件第5页浏览型号AD5342_15的Datasheet PDF文件第6页浏览型号AD5342_15的Datasheet PDF文件第7页 
AD5332/AD5333/AD5342/AD5343  
(VDD = 2.5 V to 5.5 V. RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless  
otherwise noted.)  
AC CHARACTERISTICS1  
B Version3  
Parameter2  
Min  
Typ  
Max  
Unit  
Conditions/Comments  
Output Voltage Settling Time  
AD5332  
VREF = 2 V. See Figure 20  
6
8
µs  
1/4 Scale to 3/4 Scale Change (40 H to C0 H)  
1/4 Scale to 3/4 Scale Change (100 H to 300 H)  
1/4 Scale to 3/4 Scale Change (400 H to C00 H)  
1/4 Scale to 3/4 Scale Change (400 H to C00 H)  
AD5333  
7
9
µs  
AD5342  
AD5343  
Slew Rate  
Major Code Transition Glitch Energy  
Digital Feedthrough  
Digital Crosstalk  
Analog Crosstalk  
DAC-to-DAC Crosstalk  
Multiplying Bandwidth  
Total Harmonic Distortion  
8
8
0.7  
6
0.5  
3
0.5  
3.5  
200  
–70  
10  
10  
µs  
µs  
V/µs  
nV-s  
nV-s  
nV-s  
nV-s  
nV-s  
kHz  
dB  
1 LSB Change Around Major Carry  
VREF = 2 V 0.1 V p-p. Unbuffered Mode  
VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz  
NOTES  
1Guaranteed by design and characterization, not production tested.  
2See Terminology section.  
3Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.  
Specifications subject to change without notice.  
TIMING CHARACTERISTICS1, 2, 3  
(VDD = 2.5 V to 5.5 V, All specifications TMIN to TMAX unless otherwise noted.)  
Parameter  
Limit at TMIN, TMAX  
Unit  
Condition/Comments  
t1  
0
0
20  
5
4.5  
5
5
4.5  
5
4.5  
20  
20  
50  
20  
0
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
CS to WR Setup Time  
CS to WR Hold Time  
WR Pulsewidth  
t2  
t3  
t4  
Data, GAIN, BUF, HBEN Setup Time  
Data, GAIN, BUF, HBEN Hold Time  
Synchronous Mode. WR Falling to LDAC Falling  
Synchronous Mode. LDAC Falling to WR Rising  
Synchronous Mode. WR Rising to LDAC Rising  
Asynchronous Mode. LDAC Rising to WR Rising  
Asynchronous Mode. WR Rising to LDAC Falling  
LDAC Pulsewidth  
t5  
t6  
t7  
t8  
t9  
t10  
t11  
t12  
t13  
t14  
t15  
CLR Pulsewidth  
Time Between WR Cycles  
A0 Setup Time  
A0 Hold Time  
NOTES  
1Guaranteed by design and characterization, not production tested.  
2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and  
timed from a voltage level of (VIL + VIH)/2.  
3See Figure 1.  
t1  
t2  
CS  
t13  
t3  
Specifications subject to change without notice.  
WR  
t5  
t4  
DATA,  
GAIN,  
BUF,  
HBEN  
t8  
t6  
t7  
1
LDAC  
t9  
t10  
t11  
2
LDAC  
t12  
t14  
t15  
CLR  
A0  
1
2
SYNCHRONOUS LDAC UPDATE MODE  
ASYNCHRONOUS LDAC UPDATE MODE  
Figure 1. Parallel Interface Timing Diagram  
–3–  
REV. 0  
1234567...20

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