2.5 V to 5.5 V, 115 A, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
a
AD5330/AD5331/AD5340/AD5341*
FEATURES
GENERAL DESCRIPTION
AD5330: Single 8-Bit DAC in 20-Lead TSSOP
The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and
AD5331: Single 10-Bit DAC in 20-Lead TSSOP
AD5340: Single 12-Bit DAC in 24-Lead TSSOP
AD5341: Single 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 115 A @ 3 V, 140 A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V Power Supply
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 115 µA at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both
supply rails, while the AD5330, AD5340, and AD5341 allow a
choice of buffered or unbuffered reference input.
Double-Buffered Input Logic
The AD5330/AD5331/AD5340/AD5341 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2 VREF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40؇C to +105؇C
The GAIN pin allows the output range to be set at 0 V to VREF
or 0 V to 2 × VREF
.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
The AD5330/AD5331/AD5340/AD5341 are available in Thin
Shrink Small Outline Packages (TSSOP).
Industrial Process Control
AD5330 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
V
V
DD
REF
POWER-ON
RESET
AD5330
BUF
DAC
REGISTER
INPUT
REGISTER
GAIN
8-BIT
DAC
DB
V
BUFFER
7
.
OUT
.
INTER-
FACE
LOGIC
DB
0
CS
WR
CLR
RESET
POWER-DOWN
LOGIC
LDAC
GND
PD
*Protected by U.S. Patent Number 5,969,657; other patents pending.
REV. 0
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