AD5332/AD5333/AD5342/AD5343
AD5342 FUNCTIONAL BLOCK DIAGRAM
AD5342 PIN CONFIGURATION
V
A
V
REF
DD
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB
DB
GAIN
BUF
11
10
AD5342
3
V
B
A
A
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
V
REF
REF
9
POWER-ON
RESET
DAC
REGISTER
4
V
V
8
5
OUT
7
6
5
4
3
2
1
0
12-BIT
INPUT
REGISTER
6
12-BIT
DAC
V
B
OUT
BUFFER
V
V
A
B
OUT
AD5342
DB
11
.
7
NC
NC
.
TOP VIEW
.
(Not to Scale)
DB
8
0
INTER-
FACE
9
GND
CS
LOGIC
CS
WR
A0
10
11
12
13
14
INPUT
REGISTER
12-BIT
DAC
BUFFER
OUT
WR
A0
DAC
REGISTER
CLR
DD
LDAC
PD
RESET
POWER-DOWN
LOGIC
CLR
NC = NO CONNECT
LDAC
V
B
REF
GND
PD
AD5342 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
Gain Control Pin. This controls whether the output range from the DAC is 0-VREF or 0-2 VREF.
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference Input for DAC B.
1
2
3
4
5
6
7, 8
9
10
11
12
13
14
GAIN
BUF
V
V
V
V
REFB
REFA
OUTA
OUTB
Reference Input for DAC A.
Output of DAC A. Buffered output with rail-to-rail operation.
Output of DAC B. Buffered output with rail-to-rail operation.
No Connect.
NC
GND
CS
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Address pin for selecting between DAC A and DAC B.
Asynchronous active low control input that clears all input registers and DAC registers to zeros.
Active low control input that updates the DAC registers with the contents of the input registers. This
allows all DAC outputs to be simultaneously updated.
WR
A0
CLR
LDAC
15
16
PD
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
VDD
10 F capacitor in parallel with a 0.1 F capacitor to GND.
17–28
DB0–DB11
12 Parallel Data Inputs. DB11 is the MSB of these 12 bits.
–7–
REV. 0