Datasheet > AD5342_15

AD5342_15

更新时间： 2022-02-26 12:58:04

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	327K
描述
2.5 V to 5.5 V, 230A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs

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AD5342_15 数据手册

AD5332/AD5333/AD5342/AD5343

AD5333 FUNCTIONAL BLOCK DIAGRAM

AD5333 PIN CONFIGURATION

REF

GAIN

BUF

AD5333

REF

OUT

POWER-ON

RESET

DAC

10-BIT

BUF

GAIN

AD5333

TOP VIEW

(Not to Scale)

INPUT

10-BIT

DAC

BUFFER

OUT

GND

17 DB

16 DB

15 DB

INTER-

FACE

LOGIC

A0 10

INPUT

10-BIT

DAC

BUFFER

OUT

CLR

LDAC

DAC

RESET

POWER-DOWN

LOGIC

CLR

LDAC

GND

REF

AD5333 PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

Function

Gain Control Pin. This controls whether the output range from the DAC is 0–V_REFor 0–2 V_REF.

Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.

Reference input for DAC B.

Reference input for DAC A.

Output of DAC A. Buffered output with rail-to-rail operation.

GAIN

BUF

_REFB

_REFA

_OUTA

_OUTB

Output of DAC B. Buffered output with rail-to-rail operation.

GND

Ground reference point for all circuitry on the part.

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

Address pin for selecting between DAC A and DAC B.

Asynchronous active-low control input that clears all input registers and DAC registers to zeros.

Active-low control input that updates the DAC registers with the contents of the input registers. This

allows all DAC outputs to be simultaneously updated.

CLR

LDAC

Power-Down Pin. This active low control pin puts all DACs into power-down mode.

Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

V_DD

10 ␮F capacitor in parallel with a 0.1 ␮F capacitor to GND.

15–24

DB₀–DB₉

10 Parallel Data Inputs. DB₉is the MSB of these 10 bits.

–6–

REV. 0

1...3 4 567 8 9...20

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