Datasheet > AD4632-16

AD4632-16

更新时间： 2023-12-20 18:44:57

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
51页	2023K
描述
16位、500 kSPS、双通道SAR ADC

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中文翻译

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数据手册

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AD4632-16 数据手册

Data Sheet

AD4630-16/AD4632-16

Table 46. Bit Descriptions for TEST_PAT_BYTE3

Bits

Bit Name

Description

Reset

Access

[7:0]

TEST_DATA_PAT[31:24]

32-Bit Test Pattern. Applied to both channels when OUT_DATA_MD = 4 (see the Modes Register

section).

0x5A

R/W

DIGITAL DIAGNOSTICS REGISTER

Address: 0x34, Reset: 0x40, Name: DIG_DIAG

Table 47. Bit Descriptions for DIG_DIAG

Bits

Bit Name

Description

Reset

Access

POWERUP_COMPLETED

RESET_OCCURRED

1 = Power-Up Completed. Self clearing.

0x0

0x1

Reset Occurred. This bit is set to 1 upon a reset event. Write 1 to clear (useful for detecting

brownouts).

R/W1C

[5:1]

RESERVED

Reserved.

0x0

FUSE_CRC_EN

Fuse CRC Enable. Write a 1 to force recheck of CRC.

R/W

DIGITAL ERRORS REGISTER

Address: 0x35, Reset: 0x00, Name: DIG_ERR

Table 48. Bit Descriptions for DIG_ERR

Bits

Bit Name

Description

Reset

Access

[7:1]

RESERVED

Reserved.

0x0

FUSE_CRC_ERR

Fuse CRC Error. This bit is set to 1 upon a fuse CRC error. Write 1 to clear.

R/W1C

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