Datasheet > AD4632-16

AD4632-16

更新时间： 2023-12-20 18:44:57

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
51页	2023K
描述
16位、500 kSPS、双通道SAR ADC

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数据手册

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AD4632-16 数据手册

Data Sheet

AD4630-16/AD4632-16

Table 42. Bit Descriptions for IO

Bits

Bit Name

Description

Reset

Access

[7:1]

RESERVED

IO2X

Reserved.

0x0

Double Output Driver Strength.

1 = double output driver strength.

0 = normal output driver strength.

R/W

TEST PATTERN REGISTERS

Address: 0x23, Reset: 0x0F, Name: TEST_PAT_BYTE0

Table 43. Bit Descriptions for TEST_PAT_BYTE0

Bits

Bit Name

Description

Reset

Access

[7:0]

TEST_DATA_PAT[7:0]

32-Bit Test Pattern. Applied to both channels when OUT_DATA_MD = 4 (see the Modes Register section). 0xF

R/W

Address: 0x24, Reset: 0x0F, Name: TEST_PAT_BYTE1

Table 44. Bit Descriptions for TEST_PAT_BYTE1

Bits

Bit Name

Description

Reset

Access

[7:0]

TEST_DATA_PAT[15:8]

32-Bit Test Pattern. Applied to both channels when OUT_DATA_MD = 4 (see the Modes Register

section).

0xF

R/W

Address: 0x25, Reset: 0x5A, Name: TEST_PAT_BYTE2

Table 45. Bit Descriptions for TEST_PAT_BYTE2

Bits

Bit Name

Description

Reset

Access

[7:0]

TEST_DATA_PAT[23:16]

32-Bit Test Pattern. Applied to both channels when OUT_DATA_MD = 4 (see the Modes Register

section).

0x5A

R/W

Address: 0x26, Reset: 0x5A, Name: TEST_PAT_BYTE3

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