Datasheet > AD4632-16

AD4632-16

更新时间： 2023-12-20 18:44:57

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
51页	2023K
描述
16位、500 kSPS、双通道SAR ADC

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数据手册

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AD4632-16 数据手册

Data Sheet

AD4630-16/AD4632-16

Table 40. Bit Descriptions for MODES

Bits

Bit Name

Description

Reset

Access

[7:6]

LANE_MD

Lane Mode Select.

0x0

R/W

00 = one lane per channel.

01 = two lanes per channel.

10 = four lanes per channel.

11 = Channel 0 and Channel 1 interleaved on SDO0.

Clock Mode Select.

[5:4]

CLK_MD

0x0

R/W

00 = SPI clocking mode.

01 = echo clock mode.

10 = host clock mode.

11 = invalid setting.

DDR_MD

DDR Mode Enable/Disable.

0x0

R/W

0 = SDR.

1 = DDR (only valid for echo clock and host clock modes).

Output Data Mode Select.

[2:0]

OUT_DATA_MD

000 = 16-bit differential data.

001 = 16-bit differential data + 8-bit common mode data.

010 = unused

011 = 30-bit averaged differential data + OR bit + SYNC bit.

100 = 32-bit test data pattern (see the Test Pattern Registers section).

INTERNAL OSCILLATOR REGISTER

Address: 0x21, Reset: 0x00, Name: OSCILLATOR

Table 41. Bit Descriptions for OSCILLATOR

Bits

Bit Name

Description

Reset

Access

[7:2]

OSC_LIMIT

Oscillator Limit Setting. Oscillator is limited to this number of clock pulses plus one. Automatically calculated by the

AD4630-16/AD4632-16 based on the data-word size, number of active SDO lanes, and data rate mode (SDR or DDR).

0x0

[1:0]

OSC_DIV

Oscillator Frequency Divider Setting.

00 = no divide (divide by 1).

01 = divide by 2.

0x0

R/W

10 = divide by 4.

11 = invalid setting.

OUTPUT DRIVER REGISTER

Address: 0x22, Reset: 0x00, Name: IO

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