Pseudo Differential Input, 1 MSPS/500 kSPS,
Dual, Simultaneous Sampling, 16-Bit, SAR ADCs
Data Sheet
AD4682/AD4683
FEATURES
GENERAL DESCRIPTION
Dual 16-bit ADC family
The AD4682 and the AD4683 are a 16-bit, pin-compatible family
of dual, simultaneous sampling, high speed, low power, successive
approximation register (SAR), analog-to-digital converters (ADCs)
that operate from a 3.0 V to 3.6 V power supply and feature
throughput rates up to 1 MSPS for the AD4682 and 500 kSPS
for the AD4683. The analog input type is pseudo differential
Dual simultaneous sampling
Pseudo differential analog inputs
Throughput conversion rate
1 MSPS for the AD4682
500 kSPS for the AD4683
SNR (typical)
CS
and is sampled and converted on the falling edge of
.
87.5 dB, VREF = 3.3 V external
93.4 dB with RES = 1 and OSR = ×8
On-chip oversampling function
Alert function
Resolution boost function
INL error (maximum): 2.5 LSBs
2.5 V internal reference
High speed serial interface
−40°C to +125°C operation
3 mm × 3 mm, 16-lead LFCSP
Integrated on-chip oversampling blocks improve dynamic range
and reduce noise at lower bandwidths. A buffered internal 2.5 V
reference is included. Alternatively, an external reference up to
3.3 V can be used.
The conversion process and data acquisition use standard control
inputs that allow simple interfacing to microprocessors or digital
signal processors (DSPs). The devices are compatible with
1.8 V, 2.5 V, and 3.3 V interfaces, using a separate logic supply.
COMPANION PARTS
APPLICATIONS
ADC Drivers: ADA4896-2, ADA4940-2, ADA4807-2, LTC6227
Voltage References: ADR4533 (3.3 V), ADR4525 (2.5 V)
Low Dropout Regulators: ADP166, ADP7104, ADP7182
Additional companion products on the AD4682 and AD4683
product pages
Motor control position feedback
Motor control current sense
Sonar
Power quality
Data acquisition systems
Erbium doped fiber amplifier (EDFA) applications
Inphase (I) and quadrature (Q) demodulation
Table 1. Related Devices in the Family
Input Type
16-Bit
14-Bit
12-Bit
Differential
Pseudo Differential
Single-Ended
AD7380
AD7383
AD7386
AD7381
AD7384
AD7387
AD7388
FUNCTIONAL BLOCK DIAGRAM
3.3V
3.3V
1µF
1µF
(
A A+)
IN
V
V
LOGIC
CC
VREF
C1
A
A
A+
R
IN
0V
OVER-
SAMPLING
ADC A
SDOA
A–
IN
VREF/2
REFIO
OSC
REFCAP
GND
SCLK
SDI
REF
LDO
DIGITAL
CONTROLLER
CONTROL
LOGIC
(
A B+)
IN
REGCAP
CS
VREF
0V
R
C1
A
B+
IN
OVER-
SAMPLING
ADC B
SDOB/ALERT
A
B–
IN
VREF/2
AD4682/AD4683
GND
Figure 1.
Rev. 0
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