5秒后页面跳转
74AUP1G885 PDF预览

74AUP1G885

更新时间: 2024-09-17 04:00:55
品牌 Logo 应用领域
恩智浦 - NXP 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
19页 71K
描述
Low-power dual function gate

74AUP1G885 技术参数

生命周期:ActiveReach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.57接口集成电路类型:LINE DRIVER
Base Number Matches:1

74AUP1G885 数据手册

 浏览型号74AUP1G885的Datasheet PDF文件第2页浏览型号74AUP1G885的Datasheet PDF文件第3页浏览型号74AUP1G885的Datasheet PDF文件第4页浏览型号74AUP1G885的Datasheet PDF文件第5页浏览型号74AUP1G885的Datasheet PDF文件第6页浏览型号74AUP1G885的Datasheet PDF文件第7页 
74AUP1G885  
Low-power dual function gate  
Rev. 01.00 — 26 January 2006  
Preliminary data sheet  
1. General description  
The 74AUP1G885 is a high-performance, low-power, low-voltage, Si-gate CMOS device,  
superior to most advanced CMOS compatible TTL families.  
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall  
times across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial Power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
The 74AUP1G885 provides two functions in one device.The output state of the outputs  
(1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the boolean  
funtion: 1Y = A × C. The output 2Y provides the boolean funtion: 2Y = A × B + A × C  
2. Features  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114-C Class 3A exceeds 4000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101-C exceeds 1000 V  
Low static power consumption; ICC = 0.9 µA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  

与74AUP1G885相关器件

型号 品牌 获取价格 描述 数据表
74AUP1G885DC NXP

获取价格

Low-power dual function gate
74AUP1G885DC NEXPERIA

获取价格

Low-power dual function gateProduction
74AUP1G885DC,125 NXP

获取价格

74AUP1G885 - Low-power dual function gate SSOP 8-Pin
74AUP1G885DC-G NXP

获取价格

IC AUP/ULP/V SERIES, DUAL 3-INPUT XOR GATE, PDSO8, 2.30 MM, GREEN, PLASTIC, MO-187, SOT-76
74AUP1G885GD NXP

获取价格

Low-power dual function gate
74AUP1G885GD,125 NXP

获取价格

74AUP1G885 - Low-power dual function gate SON 8-Pin
74AUP1G885GF,115 NXP

获取价格

74AUP1G885 - Low-power dual function gate SON 8-Pin
74AUP1G885GM NXP

获取价格

Low-power dual function gate
74AUP1G885GM-G NXP

获取价格

IC,LOGIC GATE,3-IN DUAL-FUNC,CMOS,LLCC,8PIN,PLASTIC
74AUP1G885GN NEXPERIA

获取价格

Low-power dual function gateProduction