Datasheet > 9FGV0641_17

9FGV0641_17

更新时间： 2024-11-20 01:04:11

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
16页	267K
描述
6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator with Zo=100ohms

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9FGV0641_17 数据手册

6-Output Very Low-Power PCIe Gen 1-2-3-4

Clock Generator with Zo=100ohms

9FGV0641

DATASHEET

Description

Features

The 9FGV0641 is a member of IDT's SOC-Friendly 1.8V very

low-power PCIe clock family. The device has integrated 100

output terminations providing direction connection to 100

transmission lines. The device also has 6 output enables for

clock management and supports 2 different spread spectrum

levels in addition to spread off.

• LP-HCSL outputs with integrated terminations; save 24

resistors compared to standard PCIe devices

• 54mW typical power consumption; reduced thermal

concerns

• Outputs can optionally be supplied from any voltage

between 1.05V and 1.8V; maximum power savings

• OE# pins; support DIF power management

• Programmable slew rate for each output; allows tuning for

various line lengths

Typical Applications

PCIe Gen1–4 clock generation for Riser Cards, Storage,

Networking, JBOD, Communications, Access Points

• Programmable output amplitude; allows tuning for various

application environments

• DIF outputs blocked until PLL is locked; clean system

Output Features

• 6 100MHz Low-Power (LP) HCSL DIF pairs with Zo =

100

• 1 1.8V LVCMOS REF output with Wake-On-LAN (WOL)

support

start-up

• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;

reduces EMI

• External 25MHz crystal; supports tight ppm with 0 ppm

synthesis error

• Configuration can be accomplished with strapping pins;

SMBus interface not required for device control

Key Specifications

• DIF cycle-to-cycle jitter <50ps

• 3.3V tolerant SMBus interface works with legacy controllers

• DIF output-to-output skew <50ps

• DIF phase jitter is PCIe Gen1-2-3-4 compliant

• REF phase jitter is <1.5ps RMS

• Selectable SMBus addresses; multiple devices can easily

share an SMBus segment

• Space saving 5 x 5 mm 40-VFQFPN; minimal board space

Block Diagram

vOE(5:0)#

REF1.8

XIN/CLKIN_25

OSC

DIF5

DIF4

SS Capable PLL

DIF3

DIF2

DIF1

DIF0

vSADR

vSS_EN_tri

^CKPWRGD_PD#

CONTROL

LOGIC

SDATA_3.3

SCLK_3.3

9FGV0641 JUNE 23, 2017

12 3 4 5 6 7...16

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