Datasheet > 9FGV1006

9FGV1006

更新时间： 2024-10-15 14:57:47

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
33页	1149K
描述
Programmable PhiClock? Generator

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9FGV1006 数据手册

PCIe Gen1–6 Low-Power

Programmable PhiClock™

Generators

9FGV1002C / 9FGV1006C

Datasheet

Description

Features

▪ 1.8V, 2.5V and/or 3.3V core power supplies

The 9FGV1002C / 9FGV1006C are members of the Renesas’

PhiClock™ programmable clock generator family. These devices

are optimized for low phase noise spread-spectrum applications

such as PCIe^®Express. Four user-defined configurations may be

selected via two hardware select pins or two I²C bits, allowing

easy software selection of the desired configuration. Any one of

the four OTP configurations may be specified as the default when

operating in I²C mode.

▪ Individual 1.8V, 2.5V or 3.3V V_DDOfor each output pair

▪ -40°C to +85°C operation – standard product

▪ -40°C to +105°C operation – 9FGV1002C automotive product

▪ Direct connection to HCSL, LVDS and LVCMOS I/O standards

▪ HCSL utilizes Renesas’ LP-HCSL technology for improved

performance, lower power and higher integration:

• Programmable output impedance of 85Ω or 100Ω

▪ Easy AC-coupling to LVPECL and CML logic – see application

note AN-891 for alternate terminations

The 9FGV1002C is available in a version targeting automotive

applications with the following characteristics:

▪ ISO9001 compliant

▪ On-board OTP supports up to 4 complete configurations

▪ AEC-Q100 qualified

▪ -40°C to +105°C (grade 2 equivalent) operation

▪ PPAP support

• 1 integer, fractional or spread spectrum output frequency

per configuration

• Configuration selected via strapping pins or I²C

▪ Internal crystal load capacitors

Compute/Networking

Applications

▪ High-performance Computing (HPC)

▪ Enterprise Storage including eSSDs

▪ 10G / 25G / 100G Ethernet

▪ Fiber Optic Modules

▪ < 125mW (9FGV1002C – 1.8V with 100MHz LP-HCSL outputs)

▪ < 100mW (9FGV1006C – 1.8V with 100MHz LP-HCSL outputs)

▪ 4 programmable I²C addresses: D0, D2, D4, D6

▪ Easily configured with Renesas Timing Commander™ software

or Web Configuration tool

▪ 4 × 4 mm 24-VFQFPN with integrated crystal option

▪ 3 × 3 mm 16-LGA with integrated crystal option

▪ NVLink

▪ Programmable spread spectrum modulation frequency and

amount

Automotive Applications

▪ Infotainment

▪ Gateway

Key Specifications

▪ Domain Controller

▪ Zone Controller

▪ 276fs RMS 12kHz–20MHz typical phase jitter at 156.25MHz

▪ PCIe Gen6 jitter (CC) < 50fs RMS

PCIe Clocking Architectures

▪ PCIe Gen1–6 Common Clocked (CC)

▪ Independent Reference (IR) without spread spectrum (SRnS)

▪ Independent Reference (IR) with spread spectrum (SRIS)

Output Features

▪ 2 or 4 programmable output pairs plus 2 LVCMOS REF outputs

▪ 1MHz–325MHz LVDS or LP-HCSL outputs

▪ 1MHz–200MHz LVCMOS outputs

June 23, 2023

12 3 4 5 6 7...33

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