8-Output Very Low-Power PCIe Gen1–4
Clock Generator with Zo = 100ohms
9FGV0841
Datasheet
Description
Features
▪ Direct connection to 100Ω transmission lines; saves 32
The 9FGV0841 is a member of IDT's SOC-friendly 1.8V very
low-power PCIe clock family. It has integrated output terminations
providing Zo = 100Ω for direction connection to 100Ω transmission
lines. The device has 8 output enables for clock management, 2
different spread spectrum levels in addition to spread off, and 2
selectable SMBus addresses.
resistors compared to standard PCIe devices
▪ 62mW typical power consumption; reduced thermal concerns
▪ Outputs can optionally be supplied from any voltage between
1.05V and 1.8V; maximum power savings
▪ OE# pins; support DIF power management
▪ LP-HCSL differential clock outputs; reduced power and board
space
Typical Applications
▪ PCIe Gen1–4 clock generation for Riser Cards
▪ Programmable slew rate for each output; allows tuning for
various line lengths
▪ Storage
▪ Networking
▪ JBOD
▪ Programmable output amplitude; allows tuning for various
application environments
▪ Communications
▪ Access Points
▪ DIF outputs blocked until PLL is locked; clean system start-up
▪ Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
Output Features
▪ Eight 100MHz Low-Power HCSL (LP-HCSL) DIF pairs with
Zo = 100Ω
▪ External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
▪ Configuration can be accomplished with strapping pins; SMBus
interface not required for device control
▪ One 1.8V LVCMOS REF output with Wake-On-LAN (WOL)
support
▪ 3.3V tolerant SMBus interface works with legacy controllers
▪ Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Key Specifications
▪ DIF cycle-to-cycle jitter < 50ps
▪ Space saving 6 × 6 mm 48-VFQFPN; minimal board space
▪ DIF output-to-output skew < 50ps
▪ DIF phase jitter is PCIe Gen1–4 compliant
▪ REF phase jitter is < 1.5ps RMS
▪ Available in Commercial (0° to +70°C), Industrial (-40°C to
+85°C) and Automotive Grade 2 (-40°C to +105°C)
temperature ranges
Block Diagram
8
vOE(7:0)#
REF1.8
XIN/CLKIN_25
OSC
DIF7
DIF6
DIF5
X2
SS Capable PLL
DIF4
DIF3
DIF2
DIF1
DIF0
vSADR
vSS_EN_tri
Control Logic
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
©2021 Renesas Electronics Corporation
1
August 20, 2021