Datasheet > 9FGV1001

9FGV1001

更新时间： 2024-09-26 14:57:23

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
28页	1375K
描述
Programmable PhiClock? Generator

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数据手册

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9FGV1001 数据手册

Low Phase-Noise, Low-Power

Programmable PhiClock™

Generators

9FGV1001C / 9FGV1005C

Datasheet

Description

Features

▪ 1.8V to 3.3V power supplies

The 9FGV1001C / 9FGV1005C are members of the Renesas

PhiClock™ programmable clock generator family. The devices are

optimized for low phase noise in non-spread spectrum

applications such as Ethernet or PCI Express. Four user-defined

configurations may be selected via two hardware select pins or

two I²C bits, allowing easy software selection of the desired

configuration.

▪ Individual 1.8V to 3.3V V_DDOfor each output pair

▪ Supports HCSL, LVDS and LVCMOS I/O standards

▪ HCSL utilizes Renesas’ LP-HCSL technology for improved

performance, lower power and higher integration:

• Programmable output impedance of 85Ω or 100Ω

▪ Supports LVPECL and CML logic with easy AC coupling. See

application note AN-891 for alternate terminations

Typical Applications

▪ On-board OTP supports up to 4 complete configurations

▪ Configuration selected via strapping pins or I²C

▪ Internal crystal load capacitors

▪ High-performance Computing (HPC)

▪ Enterprise Storage including eSSDs

▪ 10G / 25G / 100G Ethernet

▪ Data Center Accelerators

▪ < 125mW at 1.8V, LP-HCSL outputs at 100MHz (9FGV1001C)

▪ < 100mW at 1.8V, LP-HCSL outputs at 100MHz (9FGV1005C)

▪ 4 programmable I²C addresses: D0, D2, D4, D6

▪ Multiple XO replacement

PCIe Clocking Architectures

▪ Common Clocked (CC)

▪ Easily configured with Renesas Timing Commander™ software

or Web Configuration tool

▪ 4 × 4 mm 24-VFQFPN and 24-LGA packages (9FGV1001)

▪ 3 × 3 mm 16-LGA package (9FGV1005)

▪ Integrated crystal option available

▪ Independent Reference without spread spectrum (SRnS)

Output Features

▪ 9FGV1001: 4 programmable output pairs plus 2 REF outputs

▪ 9FGV1005: 2 programmable output pairs plus 1 REF output

▪ 1 integer output frequency per configuration

▪ 1MHz–325MHz differential outputs

Key Specifications

▪ 261fs RMS 12kHz–20MHz typical phase jitter at 156.25M Hz

▪ PCIe Gen5 jitter (CC) < 0.08ps RMS

▪ PCIe Gen5 jitter (SRNS) < 0.07ps RMS

▪ 1MHz–200MHz single-ended outputs

Block Diagram

VDDREFp

REF1

Consult factory if design requires REF1.

9FGV1001

XIN/CLKIN

OSC

vREF0_SEL_I2C#

OUT3#

OUT3

Prog.

Output

9FGV1001CQ and

9FGV1005CQ integrate the

crystal

VDDO3

9FGV1001

OUT2#

OUT2

Prog.

Output

INT

PLL

INT

DIV

VDDO2

OUT1#

OUT1

Prog.

Output

vSEL0/SCL

vSEL1/SDA

SMBus

Engine Configuration

Factory

VDDO1

OUT0#

OUT0

Prog.

Output

^OEB

Control

Logic

9FGV1001

^OEA

VDDO0

March 29, 2023

12 3 4 5 6 7...28

中文翻译

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与9FGV1001相关器件

型号	品牌	获取价格	描述	数据表
9FGV1002	RENESAS	获取价格	Programmable PhiClock? Generator
9FGV1004	RENESAS	获取价格	Programmable PhiClock? Generator
9FGV1005	IDT	获取价格	Low Phase-Noise, Low-Power Programmable PhiClock Generator
9FGV1005	RENESAS	获取价格	Programmable PhiClock? Generator
9FGV1005AnnnLTGI	IDT	获取价格	Low Phase-Noise, Low-Power Programmable PhiClock Generator
9FGV1005AnnnLTGI8	IDT	获取价格	Low Phase-Noise, Low-Power Programmable PhiClock Generator
9FGV1005Q5hhLTGI	IDT	获取价格	Low Phase-Noise, Low-Power Programmable PhiClock Generator
9FGV1005Q5hhLTGI8	IDT	获取价格	Low Phase-Noise, Low-Power Programmable PhiClock Generator
9FGV1006	IDT	获取价格	Low Phase-Noise, Low-Power Programmable PhiClock Generator
9FGV1006	RENESAS	获取价格	Programmable PhiClock? Generator

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