Datasheet > 9FGV0641_16

9FGV0641_16

更新时间： 2024-11-20 01:02:47

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
15页	210K
描述
6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator

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中文翻译

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数据手册

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9FGV0641_16 数据手册

6-O/P 1.8V PCIe Gen 1-2-3 Clock Generator

w/Zo=100ohms

9FGV0641

DATASHEET

General Description

Features/Benefits

The 9FGV0641 is a member of IDT's SOC-Friendly 1.8V

Very-Low-Power PCIe clock family. The device has integrated

100 ohm output terminations providing direction connection to

100 ohm transmission lines. The device also has 6 output

enables for clock management and supports 2 different

spread spectrum levels in addition to spread off.

• LP-HCSL outputs with integrated terminations; save 24

resistors compared to standard PCIe devices

• 54mW typical power consumption; reduced thermal

concerns

• Outputs can optionally be supplied from any voltage

between 1.05V and 1.8V; maximum power savings

• OE# pins; support DIF power management

• Programmable Slew rate for each output; allows tuning for

various line lengths

Recommended Application

1.8V PCIe Gen 1-2-3 Clock Generator

• Programmable output amplitude; allows tuning for various

application environments

Output Features

• 6 - 100MHz Low-Power (LP) HCSL DIF pairs w/Zo=100

• 1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)

support

• DIF outputs blocked until PLL is locked; clean system

start-up

• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;

reduces EMI

• External 25MHz crystal; supports tight ppm with 0 ppm

synthesis error

Key Specifications

• Configuration can be accomplished with strapping pins;

• DIF cycle-to-cycle jitter <50ps

SMBus interface not required for device control

• DIF output-to-output skew <50ps

• DIF phase jitter is PCIe Gen1-2-3 compliant

• REF phase jitter is <1.5ps RMS

• 3.3V tolerant SMBus interface works with legacy controllers

• Selectable SMBus addresses; multiple devices can easily

share an SMBus segment

• Space saving 40-pin 5x5 mm VFQFPN; minimal board

space

Block Diagram

vOE(5:0)#

REF1.8

XIN/CLKIN_25

OSC

DIF5

DIF4

SS Capable PLL

DIF3

DIF2

DIF1

DIF0

vSADR

vSS_EN_tri

^CKPWRGD_PD#

CONTROL

LOGIC

SDATA_3.3

SCLK_3.3

9FGV0641 OCTOBER 18, 2016

12 3 4 5 6 7...15

中文翻译

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