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9FGL0441BKILF PDF预览

9FGL0441BKILF

更新时间: 2022-02-26 10:49:51
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
18页 313K
描述
4-output 3.3V PCIe Clock Generator

9FGL0441BKILF 数据手册

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9FGL04 DATASHEET  
Electrical Characteristics–Current Consumption  
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
IDDAOP  
CONDITIONS  
MIN  
TYP  
13  
MAX  
16  
UNITS  
mA  
NOTES  
VDDA, All outputs active @100MHz  
Operating Supply Current  
All other VDD, except VDDA, All outputs active  
@100MHz  
IDDOP  
29  
40  
mA  
Wake-on-LAN Current  
(Power down state and  
Byte 3, bit 5 = '1')  
IDDAPD  
IDDPD  
VDDA, DIF outputs off, REF output running  
All other VDD, except VDDA,  
0.7  
8.8  
1.5  
14  
mA  
mA  
1
1
DIF outputs off, REF output running  
Powerdown Current  
(Power down state and  
Byte 3, bit 5 = '0')  
IDDAPD  
IDDPD  
VDDA, all outputs off  
0.7  
4.7  
1.5  
8
mA  
mA  
All other VDD, except VDDA, all outputs off  
1 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)  
Electrical Characteristics– REF  
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS Notes  
Long Accuracy  
Clock period  
ppm  
Tperiod  
see Tperiod min-max values  
REF output  
0
40  
ppm  
ns  
1,2  
2
High output Voltage  
Low output Voltage  
VHIGH  
IOH = -2mA  
0.8xVDDREF  
V
VLOW  
trf1  
IOL = 2mA  
Byte 3 = 1F, VOH = 0.8*VDD, VOL = 0.2*VDD  
Byte 3 = 5F, VOH = 0.8*VDD, VOL = 0.2*VDD  
Byte 3 = 9F, VOH = 0.8*VDD, VOL = 0.2*VDD  
Byte 3 = DF, VOH = 0.8*VDD, VOL = 0.2*VDD  
VT = VDD/2 V  
0.2xVDDREF  
1.2  
V
0.5  
1.0  
1.5  
2.0  
45  
0.9  
1.5  
V/ns  
V/ns  
V/ns  
V/ns  
%
1
trf1  
2.0  
1,3  
1
Rise/Fall Slew Rate  
trf1  
2.2  
2.6  
trf1  
2.9  
3.2  
1
Duty Cycle  
dt1X  
50.2  
-0.5  
70  
55  
1,4  
1,5  
1,4  
1,4  
1,4  
Duty Cycle Distortion  
Jitter, cycle to cycle  
dtcd  
VT = VDD/2 V  
-1  
0
%
tjcyc-cyc  
tjdBc1k  
tjdBc10k  
tjphREF  
VT = VDD/2 V  
150  
-135  
-140  
0.3  
ps  
1kHz offset  
-145  
-150  
0.13  
dBc  
dBc  
Noise floor  
10kHz offset to Nyquist  
12kHz to 5MHz, DIF SSC Off  
ps (rms) 1,4  
ps (rms) 1,4  
Jitter, phase  
tjphREF  
12kHz to 5MHz, DIF SSC On  
1.5  
2
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz  
3 Default SMBus Value  
4 When driven by a crystal.  
5 When driven by an external oscillator via the X1 pin, X2 should be floating.  
OCTOBER 19, 2016  
9
4-OUTPUT 3.3V PCIE CLOCK GENERATOR  

9FGL0441BKILF 替代型号

型号 品牌 替代类型 描述 数据表
9FGL0441BKILFT IDT

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4-output 3.3V PCIe Clock Generator

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