Datasheet > 9FGL6241

9FGL6241

更新时间： 2024-11-10 00:37:39

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
28页	536K
描述
Intelligent PCIe Clock Buffer/Generator for SSD

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中文翻译

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9FGL6241 数据手册

Intelligent PCIe Clock

Buffer/Generator for SSD

9FGL6241 / 9FGL6251

Datasheet

Description

Features

▪ Supports single or dual-ported nVME drives

The 9FGL6241 / 9FGL6251 are intelligent buffer/clock generators

tailored for single and dual-ported nVME SSDs. They support

Common (CC) and Independent Reference (IR) clocking

architectures and are ideal for U.2 and M.2 form factors. The

devices are also useful in PCIe master/slave and clock

multiplexing applications, with an internal clock generator as a

third input channel.

▪ Automatically detects presence or absence of input clocks

▪ Integrated terminations on LP-HCSL outputs save 8 resistors

▪ Choice of spread off (0% SRnS) or spread on (-0.5% SRIS)

default

▪ Choice of 25MHz or 33 1/3MHz reference clock

▪ REF clock output; saves external XO

▪ 2.5V to 3.3V operating voltage

Typical Applications

▪ 1.8V compatible, 3.3V tolerant single-ended I/O signaling

▪ Open-drain CC_IR output; maximum system flexibility

▪ 4 × 4 mm 28-VQFP-N package with external crystal

▪ 4 × 4 mm 28-LGA package with optional internal crystal

▪ 1 × 4 and 2 × 2 nVME SSDs

▪ 3:2 PCIe clock multiplexing

Output Features

▪ Two 100MHz Low-Power HCSL (LP-HCSL) outputs with Zo =

100Ω or 85Ω

Key Specifications

▪ DIF cycle-to-cycle jitter < 50ps

▪ One 33 1/3MHz or 25MHz 1.8V LVCMOS REF output

▪ One open drain CC_IR output indicates PCIe clock mode

▪ PCIe Gen1–4 (CC) compliant; Gen2–3 (IR) compliant

Block Diagram

VDDIN[A:B]

OSC

VDDDIG VDDA

VDDO1 VDDREF_1p8

XIN/CLKIN

REFOUT

PLL

DIF0#

DIF0

DIF_INA

DIF_INA#

DIF1#

DIF1

DIF_INB

DIF_INB#

Input

Detect

Logic

vePERst0#

vePERst1#

CC_IR

SCLK_3.3

SMBus Engine

Logic

POR

SDATA_3.3

Factory Configuration

GNDIN[A:B] GNDDIG

EPAD

GNDREF GNDO[0:1]

October 11, 2018

12 3 4 5 6 7...28

中文翻译

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