Datasheet > 9FGL0441BKILF

9FGL0441BKILF

更新时间： 2022-02-26 10:49:51

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
18页	313K
描述
4-output 3.3V PCIe Clock Generator

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

9FGL0441BKILF 数据手册

9FGL04 DATASHEET

Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked

(CC) Architectures

T_AMB= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

INDUSTRY

PARAMETER

SYMBOL

CONDITIONS

PCIe Gen 1

MIN

TYP

MAX

UNITS Notes

LIMIT

t_jphPCIeG1-CC

1,2,3

(p-p)

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)

PCIe Gen 3

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

PCIe Gen 4

1,2

0.5

1.3

0.6

(rms)

t_jphPCIeG2-CC

Phase Jitter

1,2

1.6

3.1

(rms)

1,2

0.50

t_jphPCIeG3-CC

0.36

(rms)

0.5

t_jphPCIeG4-CC

1,2

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

¹Applies to all outputs.

²Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisig.com for latest specifications.

³Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate

Reference Independent Spread (SRIS) Architectures³

T_AMB= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

INDUSTRY

PARAMETER

SYMBOL

t_jphPCIeG2-

CONDITIONS

MIN

TYP

MAX

UNITS Notes

LIMIT

PCIe Gen 2

(PLL BW of 16MHz , CDR = 5MHz)

1,2

0.7

1.1

(rms)

SRIS

Phase Jitter, PLL Mode

¹Applies to all outputs.

t_jphPCIeG3-

PCIe Gen 3

1,2

0.65

0.7

0.5

(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)

(rms)

SRIS

²Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest

specifications. There is a proposal to reduce the PCIe Gen3 limit to 0.5ps.

³As of PCIe Base Specification Rev4.0 draft 0.7, SRIS is not currently defined for Gen1 or Gen4.

Electrical Characteristics–DIF LP-HCSL Output Unfiltered Phase Jitter Parameters

TA = T_AMB;Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

INDUSTRY

PARAMETER

SYMBOL

t_jph12k20M

CONDITIONS

MIN

TYP

1.5

MAX

UNITS

LIMIT

N/A

100MHz outputs with REF output enabled

SSC Off

(rms)

Phase Jitter, 12k-20M

4-OUTPUT 3.3V PCIE CLOCK GENERATOR

OCTOBER 19, 2016

1...5 6 789 10 11...18

下载PDF

与9FGL0441BKILF相关器件

型号	品牌	描述	获取价格	数据表
9FGL0441BKILFT	IDT	4-output 3.3V PCIe Clock Generator	获取价格
9FGL0451BKILF	IDT	4-output 3.3V PCIe Clock Generator	获取价格
9FGL0451BKILFT	IDT	4-output 3.3V PCIe Clock Generator	获取价格
9FGL06	IDT	6-output 3.3V PCIe Clock Generator	获取价格
9FGL06	RENESAS	6-Output 3.3V PCIe Gen1–5 Clock Generator	获取价格
9FGL06_16	IDT	6-output 3.3V PCIe Clock Generator	获取价格