4-output 3.3V PCIe Clock Generator
9FGL04
DATASHEET
Description
Features/Benefits
The 9FGL04 devices are 3.3V members of IDT's 3.3V
Full-Featured PCIe family. The devices have 4 output enables
for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL04
supports PCIe Gen1-4 Common Clocked architectures (CC)
and PCIe Separate Reference no-Spread (SRnS) and
Separate Reference Independent Spread (SRIS) clocking
architectures. The 9FGL04P1 can be programmed with a
user-defined power up default SMBus configuration.
• Direct connection to 100 (xx41) or 85 (xx51)
transmission lines; saves 16 resistors compared to
standard PCIe devices
• 142mW typical power consumption (@3.3V); eliminates
thermal concerns
• SMBus-selectable features allows optimization to customer
requirements:
• control input polarity
• control input pull up/downs
• slew rate for each output
Recommended Application
• differential output amplitude
• 33, 85 or 100Ω output impedance for each output
• spread spectrum amount
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
• 4 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
• 9FGL0441 default ZOUT = 100
• 9FGL0451 default ZOUT = 85
• 9FGL04P1 factory programmable defaults
• 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
• 41 and 51 devices contain default configuration; SMBus
interface not required for device operation
• P1 device allows factory programming of customer-defined
input/output frequencies and SMBus power up default;
allows exact optimization to customer requirements.
• OE# pins; support DIF power management
• 8MHz - 40MHz input frequency with 9FGL04P1 device
(25MHz default); flexibility
• Easy AC-coupling to other logic families, see IDT
application note AN-891
• Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs %; minimize EMI and phase jitter for each
application
Key Specifications
• PCIe Gen1-2-3-4 CC-compliant
• PCIe Gen2-3 SRIS-compliant
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF 12k-20M phase jitter is <2ps rms when SSC is off
• DIF outputs blocked until PLL is locked; clean system
start-up
• Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• Space saving 32-pin 5x5mm VFQFPN; minimal board
space
• REF phase jitter is <300fs rms (SSC off) and < 1.5ps RMS
(SSC on)
• ±100ppm frequency accuracy on all clocks
Block Diagram
vOE(3:0)#
4
REF
DIF3
XIN/CLKIN_25
603-25-150JA4I 25MHz
DIF2
X2
SSC Capable
PLL
DIF1
DIF0
vSADR
vSS_EN_tri
^CKPWRGD_PD#
Control
Logic
SDATA_3.3
SCLK_3.3
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL04 OCTOBER 19, 2016
1
©2016 Integrated Device Technology, Inc.
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