Datasheet > 9FGL08

9FGL08

更新时间： 2024-11-10 01:02:43

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	402K
描述
8-output 3.3V PCIe Clock Generator

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中文翻译

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数据手册

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9FGL08 数据手册

8-output 3.3V PCIe Clock Generator

9FGL08

DATASHEET

Description

Features/Benefits

The 9FGL08 devices are 3.3V members of IDT's 3.3V

Full-Featured PCIe family. The devices have 8 output enables

for clock management and support 2 different spread

spectrum levels in addition to spread off. The 9FGL08

supports PCIe Gen1-4 Common Clocked architectures (CC)

and PCIe Separate Reference no-Spread (SRnS) and

Separate Reference Independent Spread (SRIS) clocking

architectures. The 9FGL08P1 can be programmed with a

user-defined power up default SMBus configuration.

• Direct connection to 100 (xx41) or 85 (xx51)

transmission lines; saves 32 resistors compared to

standard PCIe devices

• 206mW typical power consumption (62mA*3.3V);

eliminates thermal concerns

• SMBus-selectable features allows optimization to customer

requirements:

• control input polarity

• control input pull up/downs

• slew rate for each output

Recommended Application

• differential output amplitude

• 33, 85 or 100Ω output impedance for each output

• spread spectrum amount

PCIe Gen1-4 clock generation for Riser Cards, Storage,

Networking, JBOD, Communications, Access Points

Output Features

• 8 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs

• 9FGL0841 default ZOUT = 100

• 9FGL0851 default ZOUT = 85

• 9FGL08P1 factory programmable defaults

• 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)

support

• 41 and 51 devices contain default configuration; SMBus

interface not required for device operation

• P1 device allows factory programming of customer-defined

input/output frequencies and SMBus power up default;

allows exact optimization to customer requirements.

• 8MHz - 40MHz input frequency with 9FGL08P1 device

(25MHz default); flexibility

• OE# pins; support DIF power management

• Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF

outputs; minimize EMI and phase jitter for each application

• Easy AC-coupling to other logic families, see IDT

application note AN-891

Key Specifications

• PCIe Gen1-2-3-4 CC-compliant

• DIF outputs blocked until PLL is locked; clean system

start-up

• PCIe Gen2-3 SRIS-compliant

• DIF cycle-to-cycle jitter <50ps

• DIF output-to-output skew <50ps

• DIF 12k-20M phase jitter is <2ps rms when SSC is off

• Two selectable SMBus addresses; multiple devices can

easily share an SMBus segment

• Space saving 48-pin 6x6mm VFQFPN; minimal board

space

• REF phase jitter is <300fs rms, SSC off, and <1.5ps rms,

SSC is On

• ±100ppm frequency accuracy on all clocks

Block Diagram

vOE(7:0)#

REF

XIN/CLKIN_25

DIF7

DIF6

DIF5

603-25-150JA4I 25MHz

SSC Capable

PLL

DIF4

DIF3

DIF2

DIF1

DIF0

vSADR

vSS_EN_tri

^CKPWRGD_PD#

Control

Logic

SDATA_3.3

SCLK_3.3

Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.

9FGL08 OCTOBER 19, 2016

12 3 4 5 6 7...19

中文翻译

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