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9DBL0242BKILF PDF预览

9DBL0242BKILF

更新时间: 2024-01-06 23:58:39
品牌 Logo 应用领域
艾迪悌 - IDT PC驱动逻辑集成电路
页数 文件大小 规格书
19页 300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

9DBL0242BKILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN,针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:2.31Samacsys Description:Clock Buffer 2 O/P 3.3V PCIE ZERO DELAY BUF
系列:9DBL输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N24JESD-609代码:e3
长度:4 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:24
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4 mmBase Number Matches:1

9DBL0242BKILF 数据手册

 浏览型号9DBL0242BKILF的Datasheet PDF文件第11页浏览型号9DBL0242BKILF的Datasheet PDF文件第12页浏览型号9DBL0242BKILF的Datasheet PDF文件第13页浏览型号9DBL0242BKILF的Datasheet PDF文件第15页浏览型号9DBL0242BKILF的Datasheet PDF文件第16页浏览型号9DBL0242BKILF的Datasheet PDF文件第17页 
9DBL0242 / 9DBL0252 DATASHEET  
SMBus Table: Pull-up Pull-down Control  
Byte 15  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
X
X
X
X
X
X
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
OE1_pu/pd[1]  
OE1_pu/pd[0]  
OE1 Pull-up(PuP)/  
Pull-down(Pdwn) control  
RW  
RW  
00=None  
01=Pdwn  
10=Pup  
11 = Pup+Pdwn  
1
Note: These values are for xx42, and xx52. P2 is factory programmable.  
SMBus Table: Pull-up Pull-down Control  
Byte 16  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
X
X
1
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
CKPWRGD_PD_pu/pd[1]  
CKPWRGD_PD_pu/pd[0]  
CKPWRGD_PD Pull-up(PuP)/ RW  
00=None  
01=Pdwn  
10=Pup  
11 = Pup+Pdwn  
Pull-down(Pdwn) control  
RW  
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.  
Bytes 17 is Reserved  
SMBus Table: Polarity Control  
Byte 18  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
X
X
X
0
Reserved  
Reserved  
Sets OE1 polarity  
Sets OE0 polarity  
Reserved  
OE1_polarity  
OE0_polarity  
RW Enabled when Low Enabled when High  
RW Enabled when Low Enabled when High  
0
X
X
X
Reserved  
Reserved  
SMBus Table: Polarity Control  
Byte 19  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Name  
Control Function  
Type  
0
1
Default  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
Determines  
CKPWRGD_PD polarity  
Power Down when Power Down when  
Low High  
CKPWRGD_PD  
RW  
0
Bit 0  
2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER  
14  
FEBRUARY 8, 2017  

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