Datasheet > 9DBL06

9DBL06

更新时间： 2024-10-31 01:04:11

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	318K
描述
6-output 3.3V PCIe Zero-Delay Buffer

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中文翻译

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数据手册

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9DBL06 数据手册

6-output 3.3V PCIe Zero-Delay Buffer

9DBL06

DATASHEET

Description

Features/Benefits

The 9DBL06 devices are 3.3V members of IDT's

Full-Featured PCIe family. The 9DBL06 supports PCIe

Gen1-4 Common Clocked (CC) and PCIe Separate

Reference Independent Spread (SRIS) systems. It offers a

choice of integrated output terminations providing direct

connection to 85Ω or 100Ω transmission lines. The

9DBL06P1 can be factory programmed with a user-defined

power up default SMBus configuration.

• Direct connection to 100 (xx41) or 85 (xx51)

transmission lines; saves 24 resistors compared to

standard PCIe devices

• 149mW typical power consumption (PLL mode@3.3V);

eliminates thermal concerns

• VDDIO allows 30% power savings at optional 1.05V;

maximum power savings

• SMBus-selectable features allows optimization to customer

requirements:

Recommended Application

PCIe Gen1-4 clock distribution for Riser Cards, Storage,

Networking, JBOD, Communications, Access Points

– control input polarity

– control input pull up/downs

– slew rate for each output

Output Features

• 6 – 1-200 MHz Low-Power (LP) HCSL DIF pairs

• 9DBL0641 default ZOUT = 100

– differential output amplitude

– output impedance for each output

– 50, 100, 125MHz operating frequency

• 9DBL0651 default ZOUT = 85

• 9DBL06P1 factory programmable defaults

• Customer defined SMBus power up default can be

programmed into P1 device; allows exact optimization to

customer requirements

Key Specifications

• OE# pins; support DIF power management

• PCIe Gen1-2-3-4 CC compliant in ZDB mode

• PCIe Gen2 SRIS compliant in ZDB mode

• Supports PCIe Gen2-3 SRIS in fan-out mode

• DIF cycle-to-cycle jitter <50ps

• DIF output-to-output skew < 50ps

• Bypass mode additive phase jitter is 0 ps typical rms for

PCIe

• HCSL-compatible differential input; can be driven by

common clock sources

• Spread Spectrum tolerant; allows reduction of EMI

• Pin/SMBus selectable PLL bandwidth and PLL Bypass;

minimize phase jitter for each application

• Outputs blocked until PLL is locked; clean system start-up

• Device contains default configuration; SMBus interface not

required for device operation

• Bypass mode additive phase jitter 160fs rms typ. @

156.25M (1.5M to 10M)

• Three selectable SMBus addresses; multiple devices can

easily share an SMBus segment

• Space saving 40-pin 5x5mm VFQFPN; minimal board

space

Block Diagram

Note: Default resistors are internal on xx41/xx51 devices. P1 devices have programmable default impedances on an output-by-output basis.

9DBL06 REVISION E 06/14/16

12 3 4 5 6 7...19

中文翻译

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与9DBL06相关器件

型号	品牌	获取价格	描述	数据表
9DBL0641	IDT	获取价格	6-output 3.3V PCIe Zero-Delay Buffer
9DBL0641	RENESAS	获取价格	6-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer
9DBL0641BKILF	IDT	获取价格	6-output 3.3V PCIe Zero-Delay Buffer
9DBL0641BKILFT	IDT	获取价格	6-output 3.3V PCIe Zero-Delay Buffer
9DBL0643	RENESAS	获取价格	6-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator
9DBL0651	IDT	获取价格	6-output 3.3V PCIe Zero-Delay Buffer
9DBL0651	RENESAS	获取价格	6-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer
9DBL0651BKILF	IDT	获取价格	6-output 3.3V PCIe Zero-Delay Buffer
9DBL0651BKILFT	IDT	获取价格	6-output 3.3V PCIe Zero-Delay Buffer
9DBL0653	RENESAS	获取价格	6-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer with Loss of Signal Indicator

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